summaryrefslogtreecommitdiff
path: root/arch/sparc/isa/decoder.isa
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2006-03-14 16:08:32 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-03-14 16:08:32 -0500
commitfa763d2ecfae16e84a9f9d689d19f746d84d08e3 (patch)
tree52474edfd8d1ab010a376b1eb66f4d9990fe4a54 /arch/sparc/isa/decoder.isa
parentf045b110cf1db6f9fc70589532b48d9cca339897 (diff)
parentefe46430fac2419a02062e3b282324498a55df28 (diff)
downloadgem5-fa763d2ecfae16e84a9f9d689d19f746d84d08e3.tar.xz
Merge m5.eecs.umich.edu:/bk/newmem
into ewok.(none):/home/gblack/m5/newmem cpu/cpu_exec_context.cc: Hand merge --HG-- rename : arch/alpha/registerfile.hh => arch/alpha/regfile.hh extra : convert_revision : bd18966f7c37c67c2bc7ca2633b58f70ce64409c
Diffstat (limited to 'arch/sparc/isa/decoder.isa')
-rw-r--r--arch/sparc/isa/decoder.isa2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/sparc/isa/decoder.isa b/arch/sparc/isa/decoder.isa
index eb458211b..eaf3aab3b 100644
--- a/arch/sparc/isa/decoder.isa
+++ b/arch/sparc/isa/decoder.isa
@@ -6,7 +6,7 @@
decode OP default Trap::unknown({{IllegalInstruction}}) {
0x0: decode OP2 {
- 0x0: Trap::illtrap({{illegal_instruction}}); //ILLTRAP
+ //0x0: Trap::illtrap({{IllegalInstruction}}); //ILLTRAP
0x1: Branch::bpcc({{
switch((CC12 << 1) | CC02)
{