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authorGabe Black <gblack@eecs.umich.edu>2006-04-06 14:52:44 -0400
committerGabe Black <gblack@eecs.umich.edu>2006-04-06 14:52:44 -0400
commit6d8d6d15cdf5547740afbd41efe7c0f1d62079f3 (patch)
treead61b78dd531bd4696f00aeda36ff97b145622a2 /arch/sparc/isa/formats/integerop.isa
parenta4b31e8f6b3c8ea33a5dad3e194c9865b92b0962 (diff)
downloadgem5-6d8d6d15cdf5547740afbd41efe7c0f1d62079f3.tar.xz
Fixed up the isa description. Also added some capability to the isa_parser in the InstObjParams constructor.
arch/isa_parser.py: Expanded the capability of the InstObjParams constructor to allow adding in extra keys for use in templates. These are added as key, value tuples as optional arguements. arch/sparc/isa/base.isa: arch/sparc/isa/formats/mem.isa: arch/sparc/isa/formats/priv.isa: The genCompositeIop function is no longer needed, as this functionality is now in the InstObjParams constructor. arch/sparc/isa/decoder.isa: Fixed up alot of instructions, and fixed indentation. arch/sparc/isa/formats/integerop.isa: The genCompositeIop function is no longer needed, as this functionality is now in the InstObjParams constructor. Also changed the immediate values to be signed. base/traceflags.py: Added SPARC traceflag configs/test/hello_sparc: Recompiled without -mflat cpu/cpu_exec_context.cc: Used the regfile clear function rather than memsetting to 0. --HG-- extra : convert_revision : b9da6f264f3ebc4ce1815008dfff7f476b247ee9
Diffstat (limited to 'arch/sparc/isa/formats/integerop.isa')
-rw-r--r--arch/sparc/isa/formats/integerop.isa20
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/sparc/isa/formats/integerop.isa b/arch/sparc/isa/formats/integerop.isa
index 2c2123f86..f14f9e858 100644
--- a/arch/sparc/isa/formats/integerop.isa
+++ b/arch/sparc/isa/formats/integerop.isa
@@ -37,7 +37,7 @@ output header {{
{
}
- uint32_t imm;
+ int32_t imm;
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
@@ -57,7 +57,7 @@ output header {{
OpClass __opClass) :
IntOpImm(mnem, _machInst, __opClass)
{
- imm = SIMM10;
+ imm = sign_ext(SIMM10, 10);
}
};
@@ -72,7 +72,7 @@ output header {{
OpClass __opClass) :
IntOpImm(mnem, _machInst, __opClass)
{
- imm = SIMM13;
+ imm = sign_ext(SIMM13, 13);
}
};
@@ -195,7 +195,7 @@ output decoder {{
if(!printPseudoOps(response, pc, symtab))
{
printMnemonic(response, mnemonic);
- if (_numSrcRegs > 1)
+ if (_numSrcRegs > 0)
{
printReg(response, _srcRegIdx[0]);
for(int x = 1; x < _numSrcRegs - 1; x++)
@@ -254,14 +254,14 @@ let {{
def doIntFormat(code, ccCode, name, Name, opt_flags):
(usesImm, code, immCode,
rString, iString) = splitOutImm(code)
- iop = genCompositeIop(code, name, Name,
- 'IntOp', opt_flags, cc_code=ccCode)
+ iop = InstObjParams(name, Name, 'IntOp', code,
+ opt_flags, ("cc_code", ccCode))
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = IntOpExecute.subst(iop)
if usesImm:
- imm_iop = genCompositeIop(code, name, Name + 'Imm',
- 'IntOpImm' + iString, opt_flags, cc_code=ccCode)
+ imm_iop = InstObjParams(name, Name + 'Imm', 'IntOpImm' + iString,
+ immCode, opt_flags, ("cc_code", ccCode))
header_output += BasicDeclare.subst(imm_iop)
decoder_output += BasicConstructor.subst(imm_iop)
exec_output += IntOpExecute.subst(imm_iop)
@@ -316,8 +316,8 @@ def format IntOpCcRes(code, *opt_flags) {{
}};
def format SetHi(code, *opt_flags) {{
- iop = genCompositeIop(code, name, Name, 'SetHi',
- opt_flags, cc_code='')
+ iop = InstObjParams(name, Name, 'SetHi',
+ code, opt_flags, ("cc_code", ''))
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = IntOpExecute.subst(iop)