Hand merge. Stuff probably doesn't compile.

--HG--
rename : arch/alpha/isa_desc => arch/alpha/isa/main.isa
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux/process.cc
rename : arch/alpha/alpha_linux_process.hh => arch/alpha/linux/process.hh
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64/process.cc
rename : arch/alpha/alpha_tru64_process.hh => arch/alpha/tru64/process.hh
rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : 7d1efcedd708815d985a951f6f010fbd83dc27e8

1 files changed, 73 insertions, 0 deletions

diff --git a/arch/sparc/isa/formats/mem.isa b/arch/sparc/isa/formats/mem.isa
new file mode 100644
index 000000000..d72de47d0
--- /dev/null
+++ b/arch/sparc/isa/formats/mem.isa
@@ -0,0 +1,73 @@
+////////////////////////////////////////////////////////////////////
+//
+// Mem instructions
+//
+
+output header {{
+        /**
+         * Base class for integer operations.
+         */
+        class Mem : public SparcStaticInst
+        {
+          protected:
+
+            // Constructor
+            Mem(const char *mnem, MachInst _machInst, OpClass __opClass) :
+                SparcStaticInst(mnem, _machInst, __opClass)
+            {
+            }
+
+            std::string generateDisassembly(Addr pc,
+                    const SymbolTable *symtab) const;
+        };
+}};
+
+output decoder {{
+        std::string Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+            return "Memory instruction\n";
+        }
+}};
+
+def template MemExecute {{
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+                Trace::InstRecord *traceData) const
+        {
+            Fault fault = NoFault;
+            %(op_decl)s;
+            %(op_rd)s;
+            ea_code
+            %(code)s;
+
+            if(fault == NoFault)
+            {
+                //Write the resulting state to the execution context
+                %(op_wb)s;
+            }
+
+            return fault;
+        }
+}};
+
+// Primary format for integer operate instructions:
+def format Mem(code, *opt_flags) {{
+        orig_code = code
+        cblk = CodeBlock(code)
+        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        exec_output = MemExecute.subst(iop)
+        exec_output.replace('ea_code', 'EA = I ? (R1 + SIMM13) : R1 + R2;');
+}};
+
+def format Cas(code, *opt_flags) {{
+        orig_code = code
+        cblk = CodeBlock(code)
+        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        exec_output = MemExecute.subst(iop)
+        exec_output.replace('ea_code', 'EA = R1;');
+}};