Fixups towards compiling.

arch/alpha/types.hh:
    Moved the DependenceTags enum from types to constants.
arch/sparc/faults.cc:
arch/sparc/faults.hh:
    Corrected a misspelling of PriviledgeOpcode and PrivilegedAction.
arch/sparc/isa/formats.isa:
    Fixups towards compiling. Added a few additional instruction formats.

--HG--
extra : convert_revision : 4c5506877b71b8a5c8c45db41192cf759cdac374

7 files changed, 257 insertions, 71 deletions

diff --git a/arch/sparc/isa/formats/branch.isa b/arch/sparc/isa/formats/branch.isa
index 80101de1b..b9dc960de 100644
--- a/arch/sparc/isa/formats/branch.isa
+++ b/arch/sparc/isa/formats/branch.isa
@@ -34,7 +34,6 @@ def template BranchExecute {{
         {
             //Attempt to execute the instruction
             Fault fault = NoFault;
-            checkPriv;
 
             %(op_decl)s;
             %(op_rd)s;
@@ -57,6 +56,6 @@ def format Branch(code, *opt_flags) {{
         iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        decode_block = BasicDecode.subst(iop)
         exec_output = BranchExecute.subst(iop)
 }};
diff --git a/arch/sparc/isa/formats/integerop.isa b/arch/sparc/isa/formats/integerop.isa
index 5a9e09896..7b6bfa54d 100644
--- a/arch/sparc/isa/formats/integerop.isa
+++ b/arch/sparc/isa/formats/integerop.isa
@@ -11,13 +11,13 @@ output header {{
         {
           protected:
             // Constructor
-            IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+            IntegerOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
                 SparcStaticInst(mnem, _machInst, __opClass)
             {
             }
 
             std::string generateDisassembly(Addr pc,
-                    const SymbolTable *symtab) const;
+                const SymbolTable *symtab) const;
         };
 }};
 
@@ -25,49 +25,40 @@ output decoder {{
         std::string IntegerOp::generateDisassembly(Addr pc,
                 const SymbolTable *symtab) const
         {
-                return "Integer instruction\n";
+            return "Integer instruction\n";
         }
 }};
 
 def template IntegerExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+                Trace::InstRecord *traceData) const
         {
-                //These are set to constants when the execute method
-                //is generated
-                bool useCc = ;
-                bool checkPriv = ;
+            Fault fault;
+            //These are set to constants when the execute method
+            //is generated
+            bool useCc = ;
 
-                //Attempt to execute the instruction
-                try
-                {
-                        checkPriv;
+            %(op_decl)s;
+            %(op_rd)s;
+            %(code)s;
 
-                        %(op_decl)s;
-                        %(op_rd)s;
-                        %(code)s;
-                }
-                //If we have an exception for some reason,
-                //deal with it
-                catch(SparcException except)
-                {
-                        //Deal with exception
-                        return No_Fault;
-                }
-
-                //Write the resulting state to the execution context
+            //Write the resulting state to the execution context
+            if(fault == NoFault)
+            {
                 %(op_wb)s;
                 if(useCc)
                 {
-                        xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63);
-                        xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0);
-                        xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue;
-                        xc->regs.miscRegFile.ccrFields.iccFields.c = icValue;
-                        xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31);
-                        xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0);
-                        xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue;
-                        xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue;
+                    CcrIccN = Rd & (1 << 63);
+                    CcrIccZ = (Rd == 0);
+                    CcrIccV = ivValue;
+                    CcrIccC = icValue;
+                    CcrXccN = Rd & (1 << 31);
+                    CcrXccZ = ((Rd & 0xFFFFFFFF) == 0);
+                    CcrXccV = xvValue;
+                    CcrXccC = xcValue;
                 }
-                return No_Fault;
+            }
+            return fault;
         }
 }};
 
@@ -75,19 +66,13 @@ def template IntegerExecute {{
 def format IntegerOp(code, *opt_flags) {{
         orig_code = code
         cblk = CodeBlock(code)
-        checkPriv = (code.find('checkPriv') != -1)
-        code.replace('checkPriv', '')
-        if checkPriv:
-                code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
-        else:
-                code.replace('checkPriv;', '')
         for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
                        ('xvValue', '0'), ('xcValue', '0')):
                 code.replace(marker, value)
         iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        decode_block = BasicDecode.subst(iop)
         exec_output = IntegerExecute.subst(iop)
 }};
 
@@ -95,18 +80,12 @@ def format IntegerOp(code, *opt_flags) {{
 def format IntegerOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
         orig_code = code
         cblk = CodeBlock(code)
-        checkPriv = (code.find('checkPriv') != -1)
-        code.replace('checkPriv', '')
-        if checkPriv:
-                code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
-        else:
-                code.replace('checkPriv;', '')
         for (marker, value) in (('ivValue', ivValue), ('icValue', icValue),
                        ('xvValue', xvValue), ('xcValue', xcValue)):
                 code.replace(marker, value)
         iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        decode_block = BasicDecode.subst(iop)
         exec_output = IntegerExecute.subst(iop)
 }};
diff --git a/arch/sparc/isa/formats/mem.isa b/arch/sparc/isa/formats/mem.isa
index d72de47d0..06725eae8 100644
--- a/arch/sparc/isa/formats/mem.isa
+++ b/arch/sparc/isa/formats/mem.isa
@@ -12,7 +12,7 @@ output header {{
           protected:
 
             // Constructor
-            Mem(const char *mnem, MachInst _machInst, OpClass __opClass) :
+            Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
                 SparcStaticInst(mnem, _machInst, __opClass)
             {
             }
@@ -56,18 +56,7 @@ def format Mem(code, *opt_flags) {{
         iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        decode_block = BasicDecode.subst(iop)
         exec_output = MemExecute.subst(iop)
         exec_output.replace('ea_code', 'EA = I ? (R1 + SIMM13) : R1 + R2;');
 }};
-
-def format Cas(code, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
-        exec_output = MemExecute.subst(iop)
-        exec_output.replace('ea_code', 'EA = R1;');
-}};
diff --git a/arch/sparc/isa/formats/noop.isa b/arch/sparc/isa/formats/noop.isa
index fa4047f06..5007f5bcb 100644
--- a/arch/sparc/isa/formats/noop.isa
+++ b/arch/sparc/isa/formats/noop.isa
@@ -11,7 +11,7 @@ output header {{
         {
           protected:
             // Constructor
-            Noop(const char *mnem, MachInst _machInst, OpClass __opClass) :
+            Noop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
                 SparcStaticInst(mnem, _machInst, __opClass)
             {
             }
@@ -45,6 +45,6 @@ def format Noop(code, *opt_flags) {{
         iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        decode_block = BasicDecode.subst(iop)
         exec_output = NoopExecute.subst(iop)
 }};
diff --git a/arch/sparc/isa/formats/priv.isa b/arch/sparc/isa/formats/priv.isa
new file mode 100644
index 000000000..7c0d8a985
--- /dev/null
+++ b/arch/sparc/isa/formats/priv.isa
@@ -0,0 +1,172 @@
+////////////////////////////////////////////////////////////////////
+//
+// Privelege mode instructions
+//
+
+output header {{
+        /**
+         * Base class for privelege mode operations.
+         */
+        class Priv : public SparcStaticInst
+        {
+          protected:
+            // Constructor
+            Priv(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
+                SparcStaticInst(mnem, _machInst, __opClass)
+            {
+            }
+
+            std::string generateDisassembly(Addr pc,
+                    const SymbolTable *symtab) const;
+        };
+
+        /**
+         * Base class for user mode "tick" access.
+         */
+        class PrivTick : public SparcStaticInst
+        {
+          protected:
+            // Constructor
+            PrivTick(const char *mnem, ExtMachInst _machInst,
+                    OpClass __opClass) :
+                SparcStaticInst(mnem, _machInst, __opClass)
+            {
+            }
+
+            std::string generateDisassembly(Addr pc,
+                    const SymbolTable *symtab) const;
+        };
+
+        /**
+         * Base class for privelege mode operations with immediates.
+         */
+        class PrivImm : public Priv
+        {
+          protected:
+            // Constructor
+            PrivImm(const char *mnem, ExtMachInst _machInst,
+                    OpClass __opClass) :
+                Priv(mnem, _machInst, __opClass), imm(SIMM13)
+            {
+            }
+
+            uint32_t imm;
+        };
+
+        /**
+         * Base class for user mode "tick" access with immediates.
+         */
+        class PrivTickImm : public PrivTick
+        {
+          protected:
+            // Constructor
+            PrivTickImm(const char *mnem, ExtMachInst _machInst,
+                    OpClass __opClass) :
+                PrivTick(mnem, _machInst, __opClass), imm(SIMM13)
+            {
+            }
+
+            uint32_t imm;
+        };
+}};
+
+output decoder {{
+        std::string Priv::generateDisassembly(Addr pc,
+                const SymbolTable *symtab) const
+        {
+                return "Privileged Instruction";
+        }
+
+        std::string PrivTick::generateDisassembly(Addr pc,
+                const SymbolTable *symtab) const
+        {
+                return "Regular access to Tick";
+        }
+}};
+
+def template PrivExecute {{
+    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+            Trace::InstRecord *traceData) const
+    {
+        %(op_decl)s;
+        %(op_rd)s;
+
+        //If the processor isn't in privileged mode, fault out right away
+        if(!pstate_priv)
+            return new PrivilegedOpCode
+
+        %(code)s;
+        %(op_wb)s;
+    }
+}};
+
+def template PrivTickExecute {{
+    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+            Trace::InstRecord *traceData) const
+    {
+        %(op_decl)s;
+        %(op_rd)s;
+
+        //If the processor isn't in privileged mode, fault out right away
+        if(!pstate_priv && tick_npt)
+            return new PrivilegedAction
+
+        %(code)s;
+        %(op_wb)s;
+    }
+}};
+
+def template Rb2OrImm13Decode {{
+    {
+        return (I ? (SparcStaticInst *)(new %(class_name)sImm(machInst))
+                  : (SparcStaticInst *)(new %(class_name)s(machInst)));
+    }
+}};
+
+// Primary format for integer operate instructions:
+def format Priv(code, *opt_flags) {{
+        uses_imm = (code.find('Rs2_or_imm13') != -1)
+        if uses_imm:
+            orig_code = code
+            code = re.sub(r'Rs2_or_imm', 'Rs2', orig_code)
+            imm_code = re.sub(r'Rs2_or_imm(\.\w+)?', 'imm', orig_code)
+        cblk = CodeBlock(code)
+        iop = InstObjParams(name, Name, 'Priv', cblk, opt_flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        exec_output = PrivExecute.subst(iop)
+        if uses_imm:
+            imm_cblk = CodeBlock(imm_code)
+            imm_iop = InstObjParams(name, Name + 'Imm', 'PrivImm', imm_cblk,
+                                    opt_flags)
+            header_output += BasicDeclare.subst(imm_iop)
+            decoder_output += BasicConstructor.subst(imm_iop)
+            exec_output += PrivExecute.subst(imm_iop)
+            decode_block = Rb2OrImm13Decode.subst(iop)
+        else:
+            decode_block = BasicDecode.subst(iop)
+}};
+
+// Primary format for integer operate instructions:
+def format PrivTick(code, *opt_flags) {{
+        uses_imm = (code.find('Rs2_or_imm13') != -1)
+        if uses_imm:
+            orig_code = code
+            code = re.sub(r'Rs2_or_imm', 'Rs2', orig_code)
+            imm_code = re.sub(r'Rs2_or_imm(\.\w+)?', 'imm', orig_code)
+        cblk = CodeBlock(code)
+        iop = InstObjParams(name, Name, 'PrivTick', cblk, opt_flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        exec_output = PrivTickExecute.subst(iop)
+        if uses_imm:
+            imm_cblk = CodeBlock(imm_code)
+            imm_iop = InstObjParams(name, Name + 'Imm', 'PrivTickImm', imm_cblk,
+                                    opt_flags)
+            header_output += BasicDeclare.subst(imm_iop)
+            decoder_output += BasicConstructor.subst(imm_iop)
+            exec_output += PrivTickExecute.subst(imm_iop)
+            decode_block = Rb2OrImm13Decode.subst(iop)
+        else:
+            decode_block = BasicDecode.subst(iop)
+}};
diff --git a/arch/sparc/isa/formats/trap.isa b/arch/sparc/isa/formats/trap.isa
index ff3aadf72..935fbfe6b 100644
--- a/arch/sparc/isa/formats/trap.isa
+++ b/arch/sparc/isa/formats/trap.isa
@@ -5,14 +5,15 @@
 
 output header {{
         /**
-         * Base class for integer operations.
+         * Base class for trap instructions,
+         * or instructions that always fault.
          */
         class Trap : public SparcStaticInst
         {
           protected:
 
             // Constructor
-            Trap(const char *mnem, MachInst _machInst, OpClass __opClass) :
+            Trap(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
                 SparcStaticInst(mnem, _machInst, __opClass)
             {
             }
@@ -34,18 +35,18 @@ def template TrapExecute {{
         Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                 Trace::InstRecord *traceData) const
         {
-            //TODO: set up a software fault and return it.
-            return NoFault;
+            Fault fault = NoFault;
+            %(code)s
+            return fault;
         }
 }};
 
-// Primary format for integer operate instructions:
 def format Trap(code, *opt_flags) {{
         orig_code = code
         cblk = CodeBlock(code)
         iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        decode_block = BasicDecode.subst(iop)
         exec_output = TrapExecute.subst(iop)
 }};
diff --git a/arch/sparc/isa/formats/unknown.isa b/arch/sparc/isa/formats/unknown.isa
new file mode 100644
index 000000000..eeb2b9496
--- /dev/null
+++ b/arch/sparc/isa/formats/unknown.isa
@@ -0,0 +1,46 @@
+////////////////////////////////////////////////////////////////////
+//
+// Unknown instructions
+//
+
+output header {{
+        /**
+         * Class for Unknown/Illegal instructions
+         */
+        class Unknown : public SparcStaticInst
+        {
+          public:
+
+            // Constructor
+            Unknown(ExtMachInst _machInst) :
+                    SparcStaticInst("unknown", _machInst, No_OpClass)
+            {
+            }
+
+            %(BasicExecDeclare)s
+
+            std::string generateDisassembly(Addr pc,
+                    const SymbolTable *symtab) const;
+
+        };
+}};
+
+output decoder {{
+        std::string Unknown::generateDisassembly(Addr pc,
+                const SymbolTable *symtab) const
+        {
+            return "Unknown instruction\n";
+        }
+}};
+
+output exec {{
+        Fault Unknown::execute(%(CPU_exec_context)s *xc,
+                Trace::InstRecord *traceData) const
+        {
+            return new IllegalInstruction;
+        }
+}};
+
+def format Unknown() {{
+        decode_block = 'return new Unknown(machInst);\n'
+}};