New directory structure:

- simulator source now in 'src' subdirectory
- imported files from 'ext' repository
- support building in arbitrary places, including
outside of the source tree.  See comment at top
of SConstruct file for more details.
Regression tests are temporarily disabled; that
syetem needs more extensive revisions.

SConstruct:
    Update for new directory structure.
    Modify to support build trees that are not subdirectories
    of the source tree.  See comment at top of file for
    more details.
    Regression tests are temporarily disabled.
src/arch/SConscript:
src/arch/isa_parser.py:
src/python/SConscript:
    Update for new directory structure.

--HG--
rename : build/SConstruct => SConstruct
rename : build/default_options/ALPHA_FS => build_opts/ALPHA_FS
rename : build/default_options/ALPHA_FS_TL => build_opts/ALPHA_FS_TL
rename : build/default_options/ALPHA_SE => build_opts/ALPHA_SE
rename : build/default_options/MIPS_SE => build_opts/MIPS_SE
rename : build/default_options/SPARC_SE => build_opts/SPARC_SE
rename : Doxyfile => src/Doxyfile
rename : SConscript => src/SConscript
rename : arch/SConscript => src/arch/SConscript
rename : arch/alpha/SConscript => src/arch/alpha/SConscript
rename : arch/alpha/aout_machdep.h => src/arch/alpha/aout_machdep.h
rename : arch/alpha/arguments.cc => src/arch/alpha/arguments.cc
rename : arch/alpha/arguments.hh => src/arch/alpha/arguments.hh
rename : arch/alpha/ecoff_machdep.h => src/arch/alpha/ecoff_machdep.h
rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc
rename : arch/alpha/ev5.hh => src/arch/alpha/ev5.hh
rename : arch/alpha/faults.cc => src/arch/alpha/faults.cc
rename : arch/alpha/faults.hh => src/arch/alpha/faults.hh
rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc
rename : arch/alpha/freebsd/system.hh => src/arch/alpha/freebsd/system.hh
rename : arch/alpha/isa/branch.isa => src/arch/alpha/isa/branch.isa
rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa
rename : arch/alpha/isa/fp.isa => src/arch/alpha/isa/fp.isa
rename : arch/alpha/isa/int.isa => src/arch/alpha/isa/int.isa
rename : arch/alpha/isa/main.isa => src/arch/alpha/isa/main.isa
rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa
rename : arch/alpha/isa/opcdec.isa => src/arch/alpha/isa/opcdec.isa
rename : arch/alpha/isa/pal.isa => src/arch/alpha/isa/pal.isa
rename : arch/alpha/isa/unimp.isa => src/arch/alpha/isa/unimp.isa
rename : arch/alpha/isa/unknown.isa => src/arch/alpha/isa/unknown.isa
rename : arch/alpha/isa/util.isa => src/arch/alpha/isa/util.isa
rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh
rename : arch/alpha/linux/aligned.hh => src/arch/alpha/linux/aligned.hh
rename : arch/alpha/linux/hwrpb.hh => src/arch/alpha/linux/hwrpb.hh
rename : arch/alpha/linux/linux.cc => src/arch/alpha/linux/linux.cc
rename : arch/alpha/linux/linux.hh => src/arch/alpha/linux/linux.hh
rename : arch/alpha/linux/process.cc => src/arch/alpha/linux/process.cc
rename : arch/alpha/linux/process.hh => src/arch/alpha/linux/process.hh
rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc
rename : arch/alpha/linux/system.hh => src/arch/alpha/linux/system.hh
rename : arch/alpha/linux/thread_info.hh => src/arch/alpha/linux/thread_info.hh
rename : arch/alpha/linux/threadinfo.hh => src/arch/alpha/linux/threadinfo.hh
rename : arch/alpha/osfpal.cc => src/arch/alpha/osfpal.cc
rename : arch/alpha/osfpal.hh => src/arch/alpha/osfpal.hh
rename : arch/alpha/process.cc => src/arch/alpha/process.cc
rename : arch/alpha/process.hh => src/arch/alpha/process.hh
rename : arch/alpha/regfile.hh => src/arch/alpha/regfile.hh
rename : arch/alpha/stacktrace.cc => src/arch/alpha/stacktrace.cc
rename : arch/alpha/stacktrace.hh => src/arch/alpha/stacktrace.hh
rename : arch/alpha/system.cc => src/arch/alpha/system.cc
rename : arch/alpha/system.hh => src/arch/alpha/system.hh
rename : arch/alpha/tlb.cc => src/arch/alpha/tlb.cc
rename : arch/alpha/tlb.hh => src/arch/alpha/tlb.hh
rename : arch/alpha/tru64/process.cc => src/arch/alpha/tru64/process.cc
rename : arch/alpha/tru64/process.hh => src/arch/alpha/tru64/process.hh
rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc
rename : arch/alpha/tru64/system.hh => src/arch/alpha/tru64/system.hh
rename : arch/alpha/tru64/tru64.cc => src/arch/alpha/tru64/tru64.cc
rename : arch/alpha/tru64/tru64.hh => src/arch/alpha/tru64/tru64.hh
rename : arch/alpha/types.hh => src/arch/alpha/types.hh
rename : arch/alpha/utility.hh => src/arch/alpha/utility.hh
rename : arch/alpha/vtophys.cc => src/arch/alpha/vtophys.cc
rename : arch/alpha/vtophys.hh => src/arch/alpha/vtophys.hh
rename : arch/isa_parser.py => src/arch/isa_parser.py
rename : arch/isa_specific.hh => src/arch/isa_specific.hh
rename : arch/mips/SConscript => src/arch/mips/SConscript
rename : arch/mips/faults.cc => src/arch/mips/faults.cc
rename : arch/mips/faults.hh => src/arch/mips/faults.hh
rename : arch/mips/isa/base.isa => src/arch/mips/isa/base.isa
rename : arch/mips/isa/bitfields.isa => src/arch/mips/isa/bitfields.isa
rename : arch/mips/isa/decoder.isa => src/arch/mips/isa/decoder.isa
rename : arch/mips/isa/formats/basic.isa => src/arch/mips/isa/formats/basic.isa
rename : arch/mips/isa/formats/branch.isa => src/arch/mips/isa/formats/branch.isa
rename : arch/mips/isa/formats/formats.isa => src/arch/mips/isa/formats/formats.isa
rename : arch/mips/isa/formats/fp.isa => src/arch/mips/isa/formats/fp.isa
rename : arch/mips/isa/formats/int.isa => src/arch/mips/isa/formats/int.isa
rename : arch/mips/isa/formats/mem.isa => src/arch/mips/isa/formats/mem.isa
rename : arch/mips/isa/formats/noop.isa => src/arch/mips/isa/formats/noop.isa
rename : arch/mips/isa/formats/tlbop.isa => src/arch/mips/isa/formats/tlbop.isa
rename : arch/mips/isa/formats/trap.isa => src/arch/mips/isa/formats/trap.isa
rename : arch/mips/isa/formats/unimp.isa => src/arch/mips/isa/formats/unimp.isa
rename : arch/mips/isa/formats/unknown.isa => src/arch/mips/isa/formats/unknown.isa
rename : arch/mips/isa/formats/util.isa => src/arch/mips/isa/formats/util.isa
rename : arch/mips/isa/includes.isa => src/arch/mips/isa/includes.isa
rename : arch/mips/isa/main.isa => src/arch/mips/isa/main.isa
rename : arch/mips/isa/operands.isa => src/arch/mips/isa/operands.isa
rename : arch/mips/isa_traits.cc => src/arch/mips/isa_traits.cc
rename : arch/mips/isa_traits.hh => src/arch/mips/isa_traits.hh
rename : arch/mips/linux/linux.cc => src/arch/mips/linux/linux.cc
rename : arch/mips/linux/linux.hh => src/arch/mips/linux/linux.hh
rename : arch/mips/linux/process.cc => src/arch/mips/linux/process.cc
rename : arch/mips/linux/process.hh => src/arch/mips/linux/process.hh
rename : arch/mips/process.cc => src/arch/mips/process.cc
rename : arch/mips/process.hh => src/arch/mips/process.hh
rename : arch/mips/regfile/float_regfile.hh => src/arch/mips/regfile/float_regfile.hh
rename : arch/mips/regfile/int_regfile.hh => src/arch/mips/regfile/int_regfile.hh
rename : arch/mips/regfile/misc_regfile.hh => src/arch/mips/regfile/misc_regfile.hh
rename : arch/mips/regfile/regfile.hh => src/arch/mips/regfile/regfile.hh
rename : arch/mips/stacktrace.hh => src/arch/mips/stacktrace.hh
rename : arch/mips/types.hh => src/arch/mips/types.hh
rename : arch/mips/utility.hh => src/arch/mips/utility.hh
rename : arch/sparc/SConscript => src/arch/sparc/SConscript
rename : arch/sparc/faults.cc => src/arch/sparc/faults.cc
rename : arch/sparc/faults.hh => src/arch/sparc/faults.hh
rename : arch/sparc/isa/base.isa => src/arch/sparc/isa/base.isa
rename : arch/sparc/isa/bitfields.isa => src/arch/sparc/isa/bitfields.isa
rename : arch/sparc/isa/decoder.isa => src/arch/sparc/isa/decoder.isa
rename : arch/sparc/isa/formats.isa => src/arch/sparc/isa/formats.isa
rename : arch/sparc/isa/formats/basic.isa => src/arch/sparc/isa/formats/basic.isa
rename : arch/sparc/isa/formats/branch.isa => src/arch/sparc/isa/formats/branch.isa
rename : arch/sparc/isa/formats/integerop.isa => src/arch/sparc/isa/formats/integerop.isa
rename : arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem.isa
rename : arch/sparc/isa/formats/nop.isa => src/arch/sparc/isa/formats/nop.isa
rename : arch/sparc/isa/formats/priv.isa => src/arch/sparc/isa/formats/priv.isa
rename : arch/sparc/isa/formats/trap.isa => src/arch/sparc/isa/formats/trap.isa
rename : arch/sparc/isa/formats/unknown.isa => src/arch/sparc/isa/formats/unknown.isa
rename : arch/sparc/isa/includes.isa => src/arch/sparc/isa/includes.isa
rename : arch/sparc/isa/main.isa => src/arch/sparc/isa/main.isa
rename : arch/sparc/isa/operands.isa => src/arch/sparc/isa/operands.isa
rename : arch/sparc/isa_traits.hh => src/arch/sparc/isa_traits.hh
rename : arch/sparc/linux/linux.cc => src/arch/sparc/linux/linux.cc
rename : arch/sparc/linux/linux.hh => src/arch/sparc/linux/linux.hh
rename : arch/sparc/linux/process.cc => src/arch/sparc/linux/process.cc
rename : arch/sparc/linux/process.hh => src/arch/sparc/linux/process.hh
rename : arch/sparc/process.cc => src/arch/sparc/process.cc
rename : arch/sparc/process.hh => src/arch/sparc/process.hh
rename : arch/sparc/regfile.hh => src/arch/sparc/regfile.hh
rename : arch/sparc/solaris/process.cc => src/arch/sparc/solaris/process.cc
rename : arch/sparc/solaris/process.hh => src/arch/sparc/solaris/process.hh
rename : arch/sparc/solaris/solaris.cc => src/arch/sparc/solaris/solaris.cc
rename : arch/sparc/solaris/solaris.hh => src/arch/sparc/solaris/solaris.hh
rename : arch/sparc/stacktrace.hh => src/arch/sparc/stacktrace.hh
rename : arch/sparc/system.cc => src/arch/sparc/system.cc
rename : arch/sparc/system.hh => src/arch/sparc/system.hh
rename : arch/sparc/utility.hh => src/arch/sparc/utility.hh
rename : base/bitfield.hh => src/base/bitfield.hh
rename : base/callback.hh => src/base/callback.hh
rename : base/chunk_generator.hh => src/base/chunk_generator.hh
rename : base/circlebuf.cc => src/base/circlebuf.cc
rename : base/circlebuf.hh => src/base/circlebuf.hh
rename : base/compression/lzss_compression.cc => src/base/compression/lzss_compression.cc
rename : base/compression/lzss_compression.hh => src/base/compression/lzss_compression.hh
rename : base/compression/null_compression.hh => src/base/compression/null_compression.hh
rename : base/cprintf.cc => src/base/cprintf.cc
rename : base/cprintf.hh => src/base/cprintf.hh
rename : base/cprintf_formats.hh => src/base/cprintf_formats.hh
rename : base/crc.cc => src/base/crc.cc
rename : base/crc.hh => src/base/crc.hh
rename : base/date.cc => src/base/date.cc
rename : base/dbl_list.hh => src/base/dbl_list.hh
rename : base/endian.hh => src/base/endian.hh
rename : base/fast_alloc.cc => src/base/fast_alloc.cc
rename : base/fast_alloc.hh => src/base/fast_alloc.hh
rename : base/fenv.hh => src/base/fenv.hh
rename : base/fifo_buffer.cc => src/base/fifo_buffer.cc
rename : base/fifo_buffer.hh => src/base/fifo_buffer.hh
rename : base/hashmap.hh => src/base/hashmap.hh
rename : base/hostinfo.cc => src/base/hostinfo.cc
rename : base/hostinfo.hh => src/base/hostinfo.hh
rename : base/hybrid_pred.cc => src/base/hybrid_pred.cc
rename : base/hybrid_pred.hh => src/base/hybrid_pred.hh
rename : base/inet.cc => src/base/inet.cc
rename : base/inet.hh => src/base/inet.hh
rename : base/inifile.cc => src/base/inifile.cc
rename : base/inifile.hh => src/base/inifile.hh
rename : base/intmath.cc => src/base/intmath.cc
rename : base/intmath.hh => src/base/intmath.hh
rename : base/kgdb.h => src/base/kgdb.h
rename : base/loader/aout_object.cc => src/base/loader/aout_object.cc
rename : base/loader/aout_object.hh => src/base/loader/aout_object.hh
rename : base/loader/coff_sym.h => src/base/loader/coff_sym.h
rename : base/loader/coff_symconst.h => src/base/loader/coff_symconst.h
rename : base/loader/ecoff_object.cc => src/base/loader/ecoff_object.cc
rename : base/loader/ecoff_object.hh => src/base/loader/ecoff_object.hh
rename : base/loader/elf_object.cc => src/base/loader/elf_object.cc
rename : base/loader/elf_object.hh => src/base/loader/elf_object.hh
rename : base/loader/exec_aout.h => src/base/loader/exec_aout.h
rename : base/loader/exec_ecoff.h => src/base/loader/exec_ecoff.h
rename : base/loader/object_file.cc => src/base/loader/object_file.cc
rename : base/loader/object_file.hh => src/base/loader/object_file.hh
rename : base/loader/symtab.cc => src/base/loader/symtab.cc
rename : base/loader/symtab.hh => src/base/loader/symtab.hh
rename : base/match.cc => src/base/match.cc
rename : base/match.hh => src/base/match.hh
rename : base/misc.cc => src/base/misc.cc
rename : base/misc.hh => src/base/misc.hh
rename : base/mod_num.hh => src/base/mod_num.hh
rename : base/mysql.cc => src/base/mysql.cc
rename : base/mysql.hh => src/base/mysql.hh
rename : base/output.cc => src/base/output.cc
rename : base/output.hh => src/base/output.hh
rename : base/pollevent.cc => src/base/pollevent.cc
rename : base/pollevent.hh => src/base/pollevent.hh
rename : base/predictor.hh => src/base/predictor.hh
rename : base/random.cc => src/base/random.cc
rename : base/random.hh => src/base/random.hh
rename : base/range.cc => src/base/range.cc
rename : base/range.hh => src/base/range.hh
rename : base/refcnt.hh => src/base/refcnt.hh
rename : base/remote_gdb.cc => src/base/remote_gdb.cc
rename : base/remote_gdb.hh => src/base/remote_gdb.hh
rename : base/res_list.hh => src/base/res_list.hh
rename : base/sat_counter.cc => src/base/sat_counter.cc
rename : base/sat_counter.hh => src/base/sat_counter.hh
rename : base/sched_list.hh => src/base/sched_list.hh
rename : base/socket.cc => src/base/socket.cc
rename : base/socket.hh => src/base/socket.hh
rename : base/statistics.cc => src/base/statistics.cc
rename : base/statistics.hh => src/base/statistics.hh
rename : base/stats/events.cc => src/base/stats/events.cc
rename : base/stats/events.hh => src/base/stats/events.hh
rename : base/stats/flags.hh => src/base/stats/flags.hh
rename : base/stats/mysql.cc => src/base/stats/mysql.cc
rename : base/stats/mysql.hh => src/base/stats/mysql.hh
rename : base/stats/mysql_run.hh => src/base/stats/mysql_run.hh
rename : base/stats/output.hh => src/base/stats/output.hh
rename : base/stats/statdb.cc => src/base/stats/statdb.cc
rename : base/stats/statdb.hh => src/base/stats/statdb.hh
rename : base/stats/text.cc => src/base/stats/text.cc
rename : base/stats/text.hh => src/base/stats/text.hh
rename : base/stats/types.hh => src/base/stats/types.hh
rename : base/stats/visit.cc => src/base/stats/visit.cc
rename : base/stats/visit.hh => src/base/stats/visit.hh
rename : base/str.cc => src/base/str.cc
rename : base/str.hh => src/base/str.hh
rename : base/time.cc => src/base/time.cc
rename : base/time.hh => src/base/time.hh
rename : base/timebuf.hh => src/base/timebuf.hh
rename : base/trace.cc => src/base/trace.cc
rename : base/trace.hh => src/base/trace.hh
rename : base/traceflags.py => src/base/traceflags.py
rename : base/userinfo.cc => src/base/userinfo.cc
rename : base/userinfo.hh => src/base/userinfo.hh
rename : cpu/SConscript => src/cpu/SConscript
rename : cpu/base.cc => src/cpu/base.cc
rename : cpu/base.hh => src/cpu/base.hh
rename : cpu/base_dyn_inst.cc => src/cpu/base_dyn_inst.cc
rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh
rename : cpu/cpu_exec_context.cc => src/cpu/cpu_exec_context.cc
rename : cpu/cpu_exec_context.hh => src/cpu/cpu_exec_context.hh
rename : cpu/cpu_models.py => src/cpu/cpu_models.py
rename : cpu/exec_context.hh => src/cpu/exec_context.hh
rename : cpu/exetrace.cc => src/cpu/exetrace.cc
rename : cpu/exetrace.hh => src/cpu/exetrace.hh
rename : cpu/inst_seq.hh => src/cpu/inst_seq.hh
rename : cpu/intr_control.cc => src/cpu/intr_control.cc
rename : cpu/intr_control.hh => src/cpu/intr_control.hh
rename : cpu/memtest/memtest.cc => src/cpu/memtest/memtest.cc
rename : cpu/memtest/memtest.hh => src/cpu/memtest/memtest.hh
rename : cpu/o3/2bit_local_pred.cc => src/cpu/o3/2bit_local_pred.cc
rename : cpu/o3/2bit_local_pred.hh => src/cpu/o3/2bit_local_pred.hh
rename : cpu/o3/alpha_cpu.cc => src/cpu/o3/alpha_cpu.cc
rename : cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha_cpu.hh
rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha_cpu_builder.cc
rename : cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha_cpu_impl.hh
rename : cpu/o3/alpha_dyn_inst.cc => src/cpu/o3/alpha_dyn_inst.cc
rename : cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha_dyn_inst.hh
rename : cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha_dyn_inst_impl.hh
rename : cpu/o3/alpha_impl.hh => src/cpu/o3/alpha_impl.hh
rename : cpu/o3/alpha_params.hh => src/cpu/o3/alpha_params.hh
rename : cpu/o3/bpred_unit.cc => src/cpu/o3/bpred_unit.cc
rename : cpu/o3/bpred_unit.hh => src/cpu/o3/bpred_unit.hh
rename : cpu/o3/bpred_unit_impl.hh => src/cpu/o3/bpred_unit_impl.hh
rename : cpu/o3/btb.cc => src/cpu/o3/btb.cc
rename : cpu/o3/btb.hh => src/cpu/o3/btb.hh
rename : cpu/o3/comm.hh => src/cpu/o3/comm.hh
rename : cpu/o3/commit.cc => src/cpu/o3/commit.cc
rename : cpu/o3/commit.hh => src/cpu/o3/commit.hh
rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh
rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc
rename : cpu/o3/cpu.hh => src/cpu/o3/cpu.hh
rename : cpu/o3/cpu_policy.hh => src/cpu/o3/cpu_policy.hh
rename : cpu/o3/decode.cc => src/cpu/o3/decode.cc
rename : cpu/o3/decode.hh => src/cpu/o3/decode.hh
rename : cpu/o3/decode_impl.hh => src/cpu/o3/decode_impl.hh
rename : cpu/o3/fetch.cc => src/cpu/o3/fetch.cc
rename : cpu/o3/fetch.hh => src/cpu/o3/fetch.hh
rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh
rename : cpu/o3/free_list.cc => src/cpu/o3/free_list.cc
rename : cpu/o3/free_list.hh => src/cpu/o3/free_list.hh
rename : cpu/o3/iew.cc => src/cpu/o3/iew.cc
rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh
rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh
rename : cpu/o3/inst_queue.cc => src/cpu/o3/inst_queue.cc
rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh
rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh
rename : cpu/o3/mem_dep_unit.cc => src/cpu/o3/mem_dep_unit.cc
rename : cpu/o3/mem_dep_unit.hh => src/cpu/o3/mem_dep_unit.hh
rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh
rename : cpu/o3/ras.cc => src/cpu/o3/ras.cc
rename : cpu/o3/ras.hh => src/cpu/o3/ras.hh
rename : cpu/o3/regfile.hh => src/cpu/o3/regfile.hh
rename : cpu/o3/rename.cc => src/cpu/o3/rename.cc
rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh
rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh
rename : cpu/o3/rename_map.cc => src/cpu/o3/rename_map.cc
rename : cpu/o3/rename_map.hh => src/cpu/o3/rename_map.hh
rename : cpu/o3/rob.cc => src/cpu/o3/rob.cc
rename : cpu/o3/rob.hh => src/cpu/o3/rob.hh
rename : cpu/o3/rob_impl.hh => src/cpu/o3/rob_impl.hh
rename : cpu/o3/sat_counter.cc => src/cpu/o3/sat_counter.cc
rename : cpu/o3/sat_counter.hh => src/cpu/o3/sat_counter.hh
rename : cpu/o3/store_set.cc => src/cpu/o3/store_set.cc
rename : cpu/o3/store_set.hh => src/cpu/o3/store_set.hh
rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc
rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh
rename : cpu/op_class.cc => src/cpu/op_class.cc
rename : cpu/op_class.hh => src/cpu/op_class.hh
rename : cpu/ozone/cpu.cc => src/cpu/ozone/cpu.cc
rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh
rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh
rename : cpu/ozone/ea_list.cc => src/cpu/ozone/ea_list.cc
rename : cpu/ozone/ea_list.hh => src/cpu/ozone/ea_list.hh
rename : cpu/pc_event.cc => src/cpu/pc_event.cc
rename : cpu/pc_event.hh => src/cpu/pc_event.hh
rename : cpu/profile.cc => src/cpu/profile.cc
rename : cpu/profile.hh => src/cpu/profile.hh
rename : cpu/simple/atomic.cc => src/cpu/simple/atomic.cc
rename : cpu/simple/atomic.hh => src/cpu/simple/atomic.hh
rename : cpu/simple/base.cc => src/cpu/simple/base.cc
rename : cpu/simple/base.hh => src/cpu/simple/base.hh
rename : cpu/simple/timing.cc => src/cpu/simple/timing.cc
rename : cpu/simple/timing.hh => src/cpu/simple/timing.hh
rename : cpu/smt.hh => src/cpu/smt.hh
rename : cpu/static_inst.cc => src/cpu/static_inst.cc
rename : cpu/static_inst.hh => src/cpu/static_inst.hh
rename : cpu/trace/opt_cpu.cc => src/cpu/trace/opt_cpu.cc
rename : cpu/trace/opt_cpu.hh => src/cpu/trace/opt_cpu.hh
rename : cpu/trace/reader/ibm_reader.cc => src/cpu/trace/reader/ibm_reader.cc
rename : cpu/trace/reader/ibm_reader.hh => src/cpu/trace/reader/ibm_reader.hh
rename : cpu/trace/reader/itx_reader.cc => src/cpu/trace/reader/itx_reader.cc
rename : cpu/trace/reader/itx_reader.hh => src/cpu/trace/reader/itx_reader.hh
rename : cpu/trace/reader/m5_reader.cc => src/cpu/trace/reader/m5_reader.cc
rename : cpu/trace/reader/m5_reader.hh => src/cpu/trace/reader/m5_reader.hh
rename : cpu/trace/reader/mem_trace_reader.cc => src/cpu/trace/reader/mem_trace_reader.cc
rename : cpu/trace/reader/mem_trace_reader.hh => src/cpu/trace/reader/mem_trace_reader.hh
rename : cpu/trace/trace_cpu.cc => src/cpu/trace/trace_cpu.cc
rename : cpu/trace/trace_cpu.hh => src/cpu/trace/trace_cpu.hh
rename : dev/alpha_access.h => src/dev/alpha_access.h
rename : dev/alpha_console.cc => src/dev/alpha_console.cc
rename : dev/alpha_console.hh => src/dev/alpha_console.hh
rename : dev/baddev.cc => src/dev/baddev.cc
rename : dev/baddev.hh => src/dev/baddev.hh
rename : dev/disk_image.cc => src/dev/disk_image.cc
rename : dev/disk_image.hh => src/dev/disk_image.hh
rename : dev/etherbus.cc => src/dev/etherbus.cc
rename : dev/etherbus.hh => src/dev/etherbus.hh
rename : dev/etherdump.cc => src/dev/etherdump.cc
rename : dev/etherdump.hh => src/dev/etherdump.hh
rename : dev/etherint.cc => src/dev/etherint.cc
rename : dev/etherint.hh => src/dev/etherint.hh
rename : dev/etherlink.cc => src/dev/etherlink.cc
rename : dev/etherlink.hh => src/dev/etherlink.hh
rename : dev/etherpkt.cc => src/dev/etherpkt.cc
rename : dev/etherpkt.hh => src/dev/etherpkt.hh
rename : dev/ethertap.cc => src/dev/ethertap.cc
rename : dev/ethertap.hh => src/dev/ethertap.hh
rename : dev/ide_atareg.h => src/dev/ide_atareg.h
rename : dev/ide_ctrl.cc => src/dev/ide_ctrl.cc
rename : dev/ide_ctrl.hh => src/dev/ide_ctrl.hh
rename : dev/ide_disk.cc => src/dev/ide_disk.cc
rename : dev/ide_disk.hh => src/dev/ide_disk.hh
rename : dev/ide_wdcreg.h => src/dev/ide_wdcreg.h
rename : dev/io_device.cc => src/dev/io_device.cc
rename : dev/io_device.hh => src/dev/io_device.hh
rename : dev/isa_fake.cc => src/dev/isa_fake.cc
rename : dev/isa_fake.hh => src/dev/isa_fake.hh
rename : dev/ns_gige.cc => src/dev/ns_gige.cc
rename : dev/ns_gige.hh => src/dev/ns_gige.hh
rename : dev/ns_gige_reg.h => src/dev/ns_gige_reg.h
rename : dev/pciconfigall.cc => src/dev/pciconfigall.cc
rename : dev/pciconfigall.hh => src/dev/pciconfigall.hh
rename : dev/pcidev.cc => src/dev/pcidev.cc
rename : dev/pcidev.hh => src/dev/pcidev.hh
rename : dev/pcireg.h => src/dev/pcireg.h
rename : dev/pitreg.h => src/dev/pitreg.h
rename : dev/pktfifo.cc => src/dev/pktfifo.cc
rename : dev/pktfifo.hh => src/dev/pktfifo.hh
rename : dev/platform.cc => src/dev/platform.cc
rename : dev/platform.hh => src/dev/platform.hh
rename : dev/rtcreg.h => src/dev/rtcreg.h
rename : dev/simconsole.cc => src/dev/simconsole.cc
rename : dev/simconsole.hh => src/dev/simconsole.hh
rename : dev/simple_disk.cc => src/dev/simple_disk.cc
rename : dev/simple_disk.hh => src/dev/simple_disk.hh
rename : dev/sinic.cc => src/dev/sinic.cc
rename : dev/sinic.hh => src/dev/sinic.hh
rename : dev/sinicreg.hh => src/dev/sinicreg.hh
rename : dev/tsunami.cc => src/dev/tsunami.cc
rename : dev/tsunami.hh => src/dev/tsunami.hh
rename : dev/tsunami_cchip.cc => src/dev/tsunami_cchip.cc
rename : dev/tsunami_cchip.hh => src/dev/tsunami_cchip.hh
rename : dev/tsunami_io.cc => src/dev/tsunami_io.cc
rename : dev/tsunami_io.hh => src/dev/tsunami_io.hh
rename : dev/tsunami_pchip.cc => src/dev/tsunami_pchip.cc
rename : dev/tsunami_pchip.hh => src/dev/tsunami_pchip.hh
rename : dev/tsunamireg.h => src/dev/tsunamireg.h
rename : dev/uart.cc => src/dev/uart.cc
rename : dev/uart.hh => src/dev/uart.hh
rename : dev/uart8250.cc => src/dev/uart8250.cc
rename : dev/uart8250.hh => src/dev/uart8250.hh
rename : kern/kernel_stats.cc => src/kern/kernel_stats.cc
rename : kern/kernel_stats.hh => src/kern/kernel_stats.hh
rename : kern/linux/events.cc => src/kern/linux/events.cc
rename : kern/linux/events.hh => src/kern/linux/events.hh
rename : kern/linux/linux.hh => src/kern/linux/linux.hh
rename : kern/linux/linux_syscalls.cc => src/kern/linux/linux_syscalls.cc
rename : kern/linux/linux_syscalls.hh => src/kern/linux/linux_syscalls.hh
rename : kern/linux/printk.cc => src/kern/linux/printk.cc
rename : kern/linux/printk.hh => src/kern/linux/printk.hh
rename : kern/linux/sched.hh => src/kern/linux/sched.hh
rename : kern/solaris/solaris.hh => src/kern/solaris/solaris.hh
rename : kern/system_events.cc => src/kern/system_events.cc
rename : kern/system_events.hh => src/kern/system_events.hh
rename : kern/tru64/dump_mbuf.cc => src/kern/tru64/dump_mbuf.cc
rename : kern/tru64/dump_mbuf.hh => src/kern/tru64/dump_mbuf.hh
rename : kern/tru64/mbuf.hh => src/kern/tru64/mbuf.hh
rename : kern/tru64/printf.cc => src/kern/tru64/printf.cc
rename : kern/tru64/printf.hh => src/kern/tru64/printf.hh
rename : kern/tru64/tru64.hh => src/kern/tru64/tru64.hh
rename : kern/tru64/tru64_events.cc => src/kern/tru64/tru64_events.cc
rename : kern/tru64/tru64_events.hh => src/kern/tru64/tru64_events.hh
rename : kern/tru64/tru64_syscalls.cc => src/kern/tru64/tru64_syscalls.cc
rename : kern/tru64/tru64_syscalls.hh => src/kern/tru64/tru64_syscalls.hh
rename : mem/bridge.cc => src/mem/bridge.cc
rename : mem/bridge.hh => src/mem/bridge.hh
rename : mem/bus.cc => src/mem/bus.cc
rename : mem/bus.hh => src/mem/bus.hh
rename : mem/cache/prefetch/tagged_prefetcher_impl.hh => src/mem/cache/prefetch/tagged_prefetcher_impl.hh
rename : mem/config/prefetch.hh => src/mem/config/prefetch.hh
rename : mem/mem_object.cc => src/mem/mem_object.cc
rename : mem/mem_object.hh => src/mem/mem_object.hh
rename : mem/packet.cc => src/mem/packet.cc
rename : mem/packet.hh => src/mem/packet.hh
rename : mem/page_table.cc => src/mem/page_table.cc
rename : mem/page_table.hh => src/mem/page_table.hh
rename : mem/physical.cc => src/mem/physical.cc
rename : mem/physical.hh => src/mem/physical.hh
rename : mem/port.cc => src/mem/port.cc
rename : mem/port.hh => src/mem/port.hh
rename : mem/request.hh => src/mem/request.hh
rename : mem/translating_port.cc => src/mem/translating_port.cc
rename : mem/translating_port.hh => src/mem/translating_port.hh
rename : mem/vport.cc => src/mem/vport.cc
rename : mem/vport.hh => src/mem/vport.hh
rename : python/SConscript => src/python/SConscript
rename : python/m5/__init__.py => src/python/m5/__init__.py
rename : python/m5/config.py => src/python/m5/config.py
rename : python/m5/convert.py => src/python/m5/convert.py
rename : python/m5/multidict.py => src/python/m5/multidict.py
rename : python/m5/objects/AlphaConsole.py => src/python/m5/objects/AlphaConsole.py
rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaFullCPU.py
rename : python/m5/objects/AlphaTLB.py => src/python/m5/objects/AlphaTLB.py
rename : python/m5/objects/BadDevice.py => src/python/m5/objects/BadDevice.py
rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py
rename : python/m5/objects/BaseCache.py => src/python/m5/objects/BaseCache.py
rename : python/m5/objects/Bridge.py => src/python/m5/objects/Bridge.py
rename : python/m5/objects/Bus.py => src/python/m5/objects/Bus.py
rename : python/m5/objects/CoherenceProtocol.py => src/python/m5/objects/CoherenceProtocol.py
rename : python/m5/objects/Device.py => src/python/m5/objects/Device.py
rename : python/m5/objects/DiskImage.py => src/python/m5/objects/DiskImage.py
rename : python/m5/objects/Ethernet.py => src/python/m5/objects/Ethernet.py
rename : python/m5/objects/Ide.py => src/python/m5/objects/Ide.py
rename : python/m5/objects/IntrControl.py => src/python/m5/objects/IntrControl.py
rename : python/m5/objects/MemObject.py => src/python/m5/objects/MemObject.py
rename : python/m5/objects/MemTest.py => src/python/m5/objects/MemTest.py
rename : python/m5/objects/Pci.py => src/python/m5/objects/Pci.py
rename : python/m5/objects/PhysicalMemory.py => src/python/m5/objects/PhysicalMemory.py
rename : python/m5/objects/Platform.py => src/python/m5/objects/Platform.py
rename : python/m5/objects/Process.py => src/python/m5/objects/Process.py
rename : python/m5/objects/Repl.py => src/python/m5/objects/Repl.py
rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py
rename : python/m5/objects/SimConsole.py => src/python/m5/objects/SimConsole.py
rename : python/m5/objects/SimpleDisk.py => src/python/m5/objects/SimpleDisk.py
rename : python/m5/objects/System.py => src/python/m5/objects/System.py
rename : python/m5/objects/Tsunami.py => src/python/m5/objects/Tsunami.py
rename : python/m5/objects/Uart.py => src/python/m5/objects/Uart.py
rename : python/m5/smartdict.py => src/python/m5/smartdict.py
rename : sim/async.hh => src/sim/async.hh
rename : sim/builder.cc => src/sim/builder.cc
rename : sim/builder.hh => src/sim/builder.hh
rename : sim/byteswap.hh => src/sim/byteswap.hh
rename : sim/debug.cc => src/sim/debug.cc
rename : sim/debug.hh => src/sim/debug.hh
rename : sim/eventq.cc => src/sim/eventq.cc
rename : sim/eventq.hh => src/sim/eventq.hh
rename : sim/faults.cc => src/sim/faults.cc
rename : sim/faults.hh => src/sim/faults.hh
rename : sim/host.hh => src/sim/host.hh
rename : sim/main.cc => src/sim/main.cc
rename : sim/param.cc => src/sim/param.cc
rename : sim/param.hh => src/sim/param.hh
rename : sim/process.cc => src/sim/process.cc
rename : sim/process.hh => src/sim/process.hh
rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc
rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh
rename : sim/root.cc => src/sim/root.cc
rename : sim/serialize.cc => src/sim/serialize.cc
rename : sim/serialize.hh => src/sim/serialize.hh
rename : sim/sim_events.cc => src/sim/sim_events.cc
rename : sim/sim_events.hh => src/sim/sim_events.hh
rename : sim/sim_exit.hh => src/sim/sim_exit.hh
rename : sim/sim_object.cc => src/sim/sim_object.cc
rename : sim/sim_object.hh => src/sim/sim_object.hh
rename : sim/startup.cc => src/sim/startup.cc
rename : sim/startup.hh => src/sim/startup.hh
rename : sim/stat_control.cc => src/sim/stat_control.cc
rename : sim/stat_control.hh => src/sim/stat_control.hh
rename : sim/stats.hh => src/sim/stats.hh
rename : sim/syscall_emul.cc => src/sim/syscall_emul.cc
rename : sim/syscall_emul.hh => src/sim/syscall_emul.hh
rename : sim/system.cc => src/sim/system.cc
rename : sim/system.hh => src/sim/system.hh
rename : sim/vptr.hh => src/sim/vptr.hh
rename : test/Makefile => src/unittest/Makefile
rename : test/bitvectest.cc => src/unittest/bitvectest.cc
rename : test/circletest.cc => src/unittest/circletest.cc
rename : test/cprintftest.cc => src/unittest/cprintftest.cc
rename : test/foo.ini => src/unittest/foo.ini
rename : test/genini.py => src/unittest/genini.py
rename : test/initest.cc => src/unittest/initest.cc
rename : test/initest.ini => src/unittest/initest.ini
rename : test/lru_test.cc => src/unittest/lru_test.cc
rename : test/nmtest.cc => src/unittest/nmtest.cc
rename : test/offtest.cc => src/unittest/offtest.cc
rename : test/paramtest.cc => src/unittest/paramtest.cc
rename : test/rangetest.cc => src/unittest/rangetest.cc
rename : test/sized_test.cc => src/unittest/sized_test.cc
rename : test/stattest.cc => src/unittest/stattest.cc
rename : test/strnumtest.cc => src/unittest/strnumtest.cc
rename : test/symtest.cc => src/unittest/symtest.cc
rename : test/tokentest.cc => src/unittest/tokentest.cc
rename : test/tracetest.cc => src/unittest/tracetest.cc
extra : convert_revision : cab6a5271ca1b368193cd948e5d3dcc47ab1bd48

8 files changed, 0 insertions, 1207 deletions

diff --git a/arch/sparc/isa/formats/basic.isa b/arch/sparc/isa/formats/basic.isa
deleted file mode 100644
index 73df7617d..000000000
--- a/arch/sparc/isa/formats/basic.isa
+++ /dev/null
@@ -1,68 +0,0 @@
-
-// Declarations for execute() methods.
-def template BasicExecDeclare {{
-        Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
-}};
-
-// Basic instruction class declaration template.
-def template BasicDeclare {{
-        /**
-         * Static instruction class for "%(mnemonic)s".
-         */
-        class %(class_name)s : public %(base_class)s
-        {
-          public:
-            // Constructor.
-            %(class_name)s(MachInst machInst);
-            %(BasicExecDeclare)s
-        };
-}};
-
-// Basic instruction class constructor template.
-def template BasicConstructor {{
-        inline %(class_name)s::%(class_name)s(MachInst machInst)
-            : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
-        {
-                %(constructor)s;
-        }
-}};
-
-// Basic instruction class execute method template.
-def template BasicExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
-                Trace::InstRecord *traceData) const
-        {
-            Fault fault = NoFault;
-
-            %(fp_enable_check)s;
-            %(op_decl)s;
-            %(op_rd)s;
-            %(code)s;
-
-            if(fault == NoFault)
-            {
-                %(op_wb)s;
-            }
-            return fault;
-        }
-}};
-
-// Basic decode template.
-def template BasicDecode {{
-        return new %(class_name)s(machInst);
-}};
-
-// Basic decode template, passing mnemonic in as string arg to constructor.
-def template BasicDecodeWithMnemonic {{
-        return new %(class_name)s("%(mnemonic)s", machInst);
-}};
-
-// The most basic instruction format... used only for a few misc. insts
-def format BasicOperate(code, *flags) {{
-        iop = InstObjParams(name, Name, 'SparcStaticInst',
-                CodeBlock(code), flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecode.subst(iop)
-        exec_output = BasicExecute.subst(iop)
-}};
diff --git a/arch/sparc/isa/formats/branch.isa b/arch/sparc/isa/formats/branch.isa
deleted file mode 100644
index 37bdb9402..000000000
--- a/arch/sparc/isa/formats/branch.isa
+++ /dev/null
@@ -1,308 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Branch instructions
-//
-
-output header {{
-        /**
-         * Base class for branch operations.
-         */
-        class Branch : public SparcStaticInst
-        {
-          protected:
-            // Constructor
-            Branch(const char *mnem, MachInst _machInst, OpClass __opClass) :
-                SparcStaticInst(mnem, _machInst, __opClass)
-            {
-            }
-
-            std::string generateDisassembly(Addr pc,
-                    const SymbolTable *symtab) const;
-        };
-
-        /**
-         * Base class for branch operations with an immediate displacement.
-         */
-        class BranchDisp : public Branch
-        {
-          protected:
-            // Constructor
-            BranchDisp(const char *mnem, MachInst _machInst,
-                    OpClass __opClass) :
-                Branch(mnem, _machInst, __opClass)
-            {
-            }
-
-            std::string generateDisassembly(Addr pc,
-                    const SymbolTable *symtab) const;
-
-            int32_t disp;
-        };
-
-        /**
-         * Base class for branches with 19 bit displacements.
-         */
-        class Branch19 : public BranchDisp
-        {
-          protected:
-            // Constructor
-            Branch19(const char *mnem, MachInst _machInst,
-                    OpClass __opClass) :
-                BranchDisp(mnem, _machInst, __opClass)
-            {
-                disp = sign_ext(DISP19 << 2, 21);
-            }
-        };
-
-        /**
-         * Base class for branches with 22 bit displacements.
-         */
-        class Branch22 : public BranchDisp
-        {
-          protected:
-            // Constructor
-            Branch22(const char *mnem, MachInst _machInst,
-                    OpClass __opClass) :
-                BranchDisp(mnem, _machInst, __opClass)
-            {
-                disp = sign_ext(DISP22 << 2, 24);
-            }
-        };
-
-        /**
-         * Base class for branches with 30 bit displacements.
-         */
-        class Branch30 : public BranchDisp
-        {
-          protected:
-            // Constructor
-            Branch30(const char *mnem, MachInst _machInst,
-                    OpClass __opClass) :
-                BranchDisp(mnem, _machInst, __opClass)
-            {
-                disp = sign_ext(DISP30 << 2, 32);
-            }
-        };
-
-        /**
-         * Base class for 16bit split displacements.
-         */
-        class BranchSplit : public BranchDisp
-        {
-          protected:
-            // Constructor
-            BranchSplit(const char *mnem, MachInst _machInst,
-                    OpClass __opClass) :
-                BranchDisp(mnem, _machInst, __opClass)
-            {
-                disp = sign_ext((D16HI << 16) | (D16LO << 2), 18);
-            }
-        };
-
-        /**
-         * Base class for branches that use an immediate and a register to
-         * compute their displacements.
-         */
-        class BranchImm13 : public Branch
-        {
-          protected:
-            // Constructor
-            BranchImm13(const char *mnem, MachInst _machInst, OpClass __opClass) :
-                Branch(mnem, _machInst, __opClass), imm(sign_ext(SIMM13, 13))
-            {
-            }
-
-            std::string generateDisassembly(Addr pc,
-                    const SymbolTable *symtab) const;
-
-            int32_t imm;
-        };
-}};
-
-output decoder {{
-        std::string Branch::generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
-        {
-            std::stringstream response;
-
-            printMnemonic(response, mnemonic);
-
-            if (_numSrcRegs > 0)
-            {
-                printReg(response, _srcRegIdx[0]);
-                for(int x = 1; x < _numSrcRegs; x++)
-                {
-                    response << ", ";
-                    printReg(response, _srcRegIdx[x]);
-                }
-            }
-
-            if (_numDestRegs > 0)
-            {
-                if(_numSrcRegs > 0)
-                    response << ", ";
-                printReg(response, _destRegIdx[0]);
-            }
-
-            return response.str();
-        }
-
-        std::string BranchImm13::generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
-        {
-            std::stringstream response;
-
-            printMnemonic(response, mnemonic);
-
-            if (_numSrcRegs > 0)
-            {
-                printReg(response, _srcRegIdx[0]);
-                for(int x = 1; x < _numSrcRegs; x++)
-                {
-                    response << ", ";
-                    printReg(response, _srcRegIdx[x]);
-                }
-            }
-
-            if(_numSrcRegs > 0)
-                response << ", ";
-
-            ccprintf(response, "0x%x", imm);
-
-            if (_numDestRegs > 0)
-            {
-                response << ", ";
-                printReg(response, _destRegIdx[0]);
-            }
-
-            return response.str();
-        }
-
-        std::string BranchDisp::generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
-        {
-            std::stringstream response;
-            std::string symbol;
-            Addr symbolAddr;
-
-            Addr target = disp + pc;
-
-            printMnemonic(response, mnemonic);
-            ccprintf(response, "0x%x", target);
-
-            if(symtab->findNearestSymbol(target, symbol, symbolAddr))
-            {
-                ccprintf(response, " <%s", symbol);
-                if(symbolAddr != target)
-                    ccprintf(response, "+%d>", target - symbolAddr);
-                else
-                    ccprintf(response, ">");
-            }
-
-            return response.str();
-        }
-}};
-
-def template BranchExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
-                Trace::InstRecord *traceData) const
-        {
-            //Attempt to execute the instruction
-            Fault fault = NoFault;
-
-            %(op_decl)s;
-            %(op_rd)s;
-
-            NNPC = xc->readNextNPC();
-            %(code)s;
-
-            if(fault == NoFault)
-            {
-                //Write the resulting state to the execution context
-                %(op_wb)s;
-            }
-
-            return fault;
-        }
-}};
-
-let {{
-    handle_annul = '''
-    {
-        if(A)
-        {
-            NPC = xc->readNextNPC();
-            NNPC = NPC + 4;
-        }
-        else
-        {
-            NPC = xc->readNextPC();
-            NNPC = xc->readNextNPC();
-        }
-    }'''
-}};
-
-// Primary format for branch instructions:
-def format Branch(code, *opt_flags) {{
-        code = re.sub(r'handle_annul', handle_annul, code)
-        (usesImm, code, immCode,
-         rString, iString) = splitOutImm(code)
-        iop = InstObjParams(name, Name, 'Branch', code, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        exec_output = BranchExecute.subst(iop)
-        if usesImm:
-            imm_iop = InstObjParams(name, Name + 'Imm', 'BranchImm' + iString,
-                    immCode, opt_flags)
-            header_output += BasicDeclare.subst(imm_iop)
-            decoder_output += BasicConstructor.subst(imm_iop)
-            exec_output += BranchExecute.subst(imm_iop)
-            decode_block = ROrImmDecode.subst(iop)
-        else:
-            decode_block = BasicDecode.subst(iop)
-}};
-
-// Primary format for branch instructions:
-def format Branch19(code, *opt_flags) {{
-        code = re.sub(r'handle_annul', handle_annul, code)
-        codeBlk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'Branch19', codeBlk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        exec_output = BranchExecute.subst(iop)
-        decode_block = BasicDecode.subst(iop)
-}};
-
-// Primary format for branch instructions:
-def format Branch22(code, *opt_flags) {{
-        code = re.sub(r'handle_annul', handle_annul, code)
-        codeBlk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'Branch22', codeBlk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        exec_output = BranchExecute.subst(iop)
-        decode_block = BasicDecode.subst(iop)
-}};
-
-// Primary format for branch instructions:
-def format Branch30(code, *opt_flags) {{
-        code = re.sub(r'handle_annul', handle_annul, code)
-        codeBlk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'Branch30', codeBlk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        exec_output = BranchExecute.subst(iop)
-        decode_block = BasicDecode.subst(iop)
-}};
-
-// Primary format for branch instructions:
-def format BranchSplit(code, *opt_flags) {{
-        code = re.sub(r'handle_annul', handle_annul, code)
-        codeBlk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'BranchSplit', codeBlk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        exec_output = BranchExecute.subst(iop)
-        decode_block = BasicDecode.subst(iop)
-}};
-
diff --git a/arch/sparc/isa/formats/integerop.isa b/arch/sparc/isa/formats/integerop.isa
deleted file mode 100644
index 881154b67..000000000
--- a/arch/sparc/isa/formats/integerop.isa
+++ /dev/null
@@ -1,349 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Integer operate instructions
-//
-
-output header {{
-        /**
-         * Base class for integer operations.
-         */
-        class IntOp : public SparcStaticInst
-        {
-          protected:
-            // Constructor
-            IntOp(const char *mnem, ExtMachInst _machInst,
-                    OpClass __opClass) :
-                SparcStaticInst(mnem, _machInst, __opClass)
-            {
-            }
-
-            std::string generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const;
-
-            virtual bool printPseudoOps(std::ostream &os, Addr pc,
-                    const SymbolTable *symtab) const;
-        };
-
-        /**
-         * Base class for immediate integer operations.
-         */
-        class IntOpImm : public IntOp
-        {
-          protected:
-            // Constructor
-            IntOpImm(const char *mnem, ExtMachInst _machInst,
-                    OpClass __opClass) :
-                IntOp(mnem, _machInst, __opClass)
-            {
-            }
-
-            int32_t imm;
-
-            std::string generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const;
-
-            virtual bool printPseudoOps(std::ostream &os, Addr pc,
-                    const SymbolTable *symtab) const;
-        };
-
-        /**
-         * Base class for 10 bit immediate integer operations.
-         */
-        class IntOpImm10 : public IntOpImm
-        {
-          protected:
-            // Constructor
-            IntOpImm10(const char *mnem, ExtMachInst _machInst,
-                    OpClass __opClass) :
-                IntOpImm(mnem, _machInst, __opClass)
-            {
-                imm = sign_ext(SIMM10, 10);
-            }
-        };
-
-        /**
-         * Base class for 11 bit immediate integer operations.
-         */
-        class IntOpImm11 : public IntOpImm
-        {
-          protected:
-            // Constructor
-            IntOpImm11(const char *mnem, ExtMachInst _machInst,
-                    OpClass __opClass) :
-                IntOpImm(mnem, _machInst, __opClass)
-            {
-                imm = sign_ext(SIMM11, 11);
-            }
-        };
-
-        /**
-         * Base class for 13 bit immediate integer operations.
-         */
-        class IntOpImm13 : public IntOpImm
-        {
-          protected:
-            // Constructor
-            IntOpImm13(const char *mnem, ExtMachInst _machInst,
-                    OpClass __opClass) :
-                IntOpImm(mnem, _machInst, __opClass)
-            {
-                imm = sign_ext(SIMM13, 13);
-            }
-        };
-
-        /**
-         * Base class for sethi.
-         */
-        class SetHi : public IntOpImm
-        {
-          protected:
-            // Constructor
-            SetHi(const char *mnem, ExtMachInst _machInst,
-                    OpClass __opClass) :
-                IntOpImm(mnem, _machInst, __opClass)
-            {
-                imm = (IMM22 << 10) & 0xFFFFFC00;
-            }
-
-            std::string generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const;
-        };
-}};
-
-def template SetHiDecode {{
-    {
-        if(RD == 0 && IMM22 == 0)
-            return (SparcStaticInst *)(new Nop("nop", machInst, No_OpClass));
-        else
-            return (SparcStaticInst *)(new %(class_name)s(machInst));
-    }
-}};
-
-output decoder {{
-
-        bool IntOp::printPseudoOps(std::ostream &os, Addr pc,
-                const SymbolTable *symbab) const
-        {
-            if(!strcmp(mnemonic, "or") && _srcRegIdx[0] == 0)
-            {
-                printMnemonic(os, "mov");
-                if(_numSrcRegs > 0)
-                    printReg(os, _srcRegIdx[1]);
-                ccprintf(os, ", ");
-                if(_numDestRegs > 0)
-                    printReg(os, _destRegIdx[0]);
-
-                return true;
-            }
-            return false;
-        }
-
-        bool IntOpImm::printPseudoOps(std::ostream &os, Addr pc,
-                const SymbolTable *symbab) const
-        {
-            if(!strcmp(mnemonic, "or"))
-            {
-                if(_srcRegIdx[0] == 0)
-                {
-                    if(imm == 0)
-                    {
-                        printMnemonic(os, "clr");
-                        if(_numDestRegs > 0)
-                            printReg(os, _destRegIdx[0]);
-                        return true;
-                    }
-                    else
-                    {
-                        printMnemonic(os, "mov");
-                        ccprintf(os, ", 0x%x, ", imm);
-                        if(_numDestRegs > 0)
-                            printReg(os, _destRegIdx[0]);
-                        return true;
-                    }
-                }
-                else if(imm == 0)
-                {
-                    printMnemonic(os, "mov");
-                    if(_numSrcRegs > 0)
-                        printReg(os, _srcRegIdx[0]);
-                    ccprintf(os, ", ");
-                    if(_numDestRegs > 0)
-                        printReg(os, _destRegIdx[0]);
-                    return true;
-                }
-            }
-            return false;
-        }
-
-        std::string IntOp::generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
-        {
-            std::stringstream response;
-
-            if(!printPseudoOps(response, pc, symtab))
-            {
-                printMnemonic(response, mnemonic);
-                if (_numSrcRegs > 0)
-                {
-                    printReg(response, _srcRegIdx[0]);
-                    for(int x = 1; x < _numSrcRegs; x++)
-                    {
-                        response << ", ";
-                        printReg(response, _srcRegIdx[x]);
-                    }
-                }
-                if (_numDestRegs > 0)
-                {
-                    if(_numSrcRegs > 0)
-                        response << ", ";
-                    printReg(response, _destRegIdx[0]);
-                }
-            }
-            return response.str();
-        }
-
-        std::string IntOpImm::generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
-        {
-            std::stringstream response;
-
-            if(!printPseudoOps(response, pc, symtab))
-            {
-                printMnemonic(response, mnemonic);
-                if (_numSrcRegs > 0)
-                {
-                    printReg(response, _srcRegIdx[0]);
-                    for(int x = 1; x < _numSrcRegs - 1; x++)
-                    {
-                        response << ", ";
-                        printReg(response, _srcRegIdx[x]);
-                    }
-                }
-                if(_numSrcRegs > 0)
-                    response << ", ";
-                ccprintf(response, "0x%x", imm);
-                if (_numDestRegs > 0)
-                {
-                    response << ", ";
-                    printReg(response, _destRegIdx[0]);
-                }
-            }
-            return response.str();
-        }
-
-        std::string SetHi::generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
-        {
-            std::stringstream response;
-
-            printMnemonic(response, mnemonic);
-            if(_numSrcRegs > 0)
-                response << ", ";
-            ccprintf(response, "%%hi(0x%x), ", imm);
-            printReg(response, _destRegIdx[0]);
-            return response.str();
-        }
-}};
-
-def template IntOpExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
-                Trace::InstRecord *traceData) const
-        {
-            Fault fault = NoFault;
-
-            %(op_decl)s;
-            %(op_rd)s;
-            %(code)s;
-
-            //Write the resulting state to the execution context
-            if(fault == NoFault)
-            {
-                %(cc_code)s;
-                %(op_wb)s;
-            }
-            return fault;
-        }
-}};
-
-let {{
-    def doIntFormat(code, ccCode, name, Name, opt_flags):
-        (usesImm, code, immCode,
-         rString, iString) = splitOutImm(code)
-        iop = InstObjParams(name, Name,	'IntOp', code,
-                opt_flags, ("cc_code", ccCode))
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        exec_output = IntOpExecute.subst(iop)
-        if usesImm:
-            imm_iop = InstObjParams(name, Name + 'Imm', 'IntOpImm' + iString,
-                    immCode, opt_flags, ("cc_code", ccCode))
-            header_output += BasicDeclare.subst(imm_iop)
-            decoder_output += BasicConstructor.subst(imm_iop)
-            exec_output += IntOpExecute.subst(imm_iop)
-            decode_block = ROrImmDecode.subst(iop)
-        else:
-            decode_block = BasicDecode.subst(iop)
-        return (header_output, decoder_output, exec_output, decode_block)
-
-    calcCcCode = '''
-        CcrIccN = (Rd >> 31) & 1;
-        CcrIccZ = ((Rd & 0xFFFFFFFF) == 0);
-        CcrXccN = (Rd >> 63) & 1;
-        CcrXccZ = (Rd == 0);
-        CcrIccV = %(ivValue)s;
-        CcrIccC = %(icValue)s;
-        CcrXccV = %(xvValue)s;
-        CcrXccC = %(xcValue)s;
-        DPRINTF(Sparc, "in = %%d\\n", CcrIccN);
-        DPRINTF(Sparc, "iz = %%d\\n", CcrIccZ);
-        DPRINTF(Sparc, "xn = %%d\\n", CcrXccN);
-        DPRINTF(Sparc, "xz = %%d\\n", CcrXccZ);
-        DPRINTF(Sparc, "iv = %%d\\n", CcrIccV);
-        DPRINTF(Sparc, "ic = %%d\\n", CcrIccC);
-        DPRINTF(Sparc, "xv = %%d\\n", CcrXccV);
-        DPRINTF(Sparc, "xc = %%d\\n", CcrXccC);
-        '''
-}};
-
-// Primary format for integer operate instructions:
-def format IntOp(code, *opt_flags) {{
-    ccCode = ''
-    (header_output,
-     decoder_output,
-     exec_output,
-     decode_block) = doIntFormat(code, ccCode,
-                                 name, Name, opt_flags)
-}};
-
-// Primary format for integer operate instructions:
-def format IntOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
-    ccCode = calcCcCode % vars()
-    (header_output,
-     decoder_output,
-     exec_output,
-     decode_block) = doIntFormat(code, ccCode,
-                                 name, Name, opt_flags)
-}};
-
-// Primary format for integer operate instructions:
-def format IntOpCcRes(code, *opt_flags) {{
-    ccCode = calcCcCode % {"icValue":"0",
-                        "ivValue":"0",
-                        "xcValue":"0",
-                        "xvValue":"0"}
-    (header_output,
-     decoder_output,
-     exec_output,
-     decode_block) = doIntFormat(code, ccCode,
-                                 name, Name, opt_flags)
-}};
-
-def format SetHi(code, *opt_flags) {{
-    iop = InstObjParams(name, Name, 'SetHi',
-            code, opt_flags, ("cc_code", ''))
-    header_output = BasicDeclare.subst(iop)
-    decoder_output = BasicConstructor.subst(iop)
-    exec_output = IntOpExecute.subst(iop)
-    decode_block = SetHiDecode.subst(iop)
-}};
-
diff --git a/arch/sparc/isa/formats/mem.isa b/arch/sparc/isa/formats/mem.isa
deleted file mode 100644
index 12dae57e5..000000000
--- a/arch/sparc/isa/formats/mem.isa
+++ /dev/null
@@ -1,171 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Mem instructions
-//
-
-output header {{
-        /**
-         * Base class for memory operations.
-         */
-        class Mem : public SparcStaticInst
-        {
-          protected:
-
-            // Constructor
-            Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
-                SparcStaticInst(mnem, _machInst, __opClass)
-            {
-            }
-
-            std::string generateDisassembly(Addr pc,
-                    const SymbolTable *symtab) const;
-        };
-
-        /**
-         * Class for memory operations which use an immediate offset.
-         */
-        class MemImm : public Mem
-        {
-          protected:
-
-            // Constructor
-            MemImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
-                Mem(mnem, _machInst, __opClass)
-            {
-                imm = sign_ext(SIMM13, 13);
-            }
-
-            std::string generateDisassembly(Addr pc,
-                    const SymbolTable *symtab) const;
-
-            int32_t imm;
-        };
-}};
-
-output decoder {{
-        std::string Mem::generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
-        {
-            std::stringstream response;
-            bool load = flags[IsLoad];
-            bool save = flags[IsStore];
-
-            printMnemonic(response, mnemonic);
-            if(save)
-            {
-                printReg(response, _srcRegIdx[0]);
-                ccprintf(response, ", ");
-            }
-            ccprintf(response, "[ ");
-            printReg(response, _srcRegIdx[!save ? 0 : 1]);
-            ccprintf(response, " + ");
-            printReg(response, _srcRegIdx[!save ? 1 : 2]);
-            ccprintf(response, " ]");
-            if(load)
-            {
-                ccprintf(response, ", ");
-                printReg(response, _destRegIdx[0]);
-            }
-
-            return response.str();
-        }
-
-        std::string MemImm::generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
-        {
-            std::stringstream response;
-            bool load = flags[IsLoad];
-            bool save = flags[IsStore];
-
-            printMnemonic(response, mnemonic);
-            if(save)
-            {
-                printReg(response, _srcRegIdx[0]);
-                ccprintf(response, ", ");
-            }
-            ccprintf(response, "[ ");
-            printReg(response, _srcRegIdx[!save ? 0 : 1]);
-            if(imm >= 0)
-                ccprintf(response, " + 0x%x ]", imm);
-            else
-                ccprintf(response, " + -0x%x ]", -imm);
-            if(load)
-            {
-                ccprintf(response, ", ");
-                printReg(response, _destRegIdx[0]);
-            }
-
-            return response.str();
-        }
-}};
-
-def template MemExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
-                Trace::InstRecord *traceData) const
-        {
-            Fault fault = NoFault;
-            Addr EA;
-            %(op_decl)s;
-            %(op_rd)s;
-            %(ea_code)s;
-            DPRINTF(Sparc, "The address is 0x%x\n", EA);
-            %(load)s;
-            %(code)s;
-            %(store)s;
-
-            if(fault == NoFault)
-            {
-                //Write the resulting state to the execution context
-                %(op_wb)s;
-            }
-
-            return fault;
-        }
-}};
-
-let {{
-    # Leave memAccessFlags at 0 for now
-    loadString = "xc->read(EA, (uint%(width)s_t&)Mem, 0);"
-    storeString = "uint64_t write_result = 0; \
-    xc->write((uint%(width)s_t)Mem, EA, 0, &write_result);"
-
-    def doMemFormat(code, load, store, name, Name, opt_flags):
-        addrCalcReg = 'EA = Rs1 + Rs2;'
-        addrCalcImm = 'EA = Rs1 + imm;'
-        iop = InstObjParams(name, Name, 'Mem', code,
-                opt_flags, ("ea_code", addrCalcReg),
-                ("load", load), ("store", store))
-        iop_imm = InstObjParams(name, Name + 'Imm', 'MemImm', code,
-                opt_flags, ("ea_code", addrCalcImm),
-                ("load", load), ("store", store))
-        header_output = BasicDeclare.subst(iop) + BasicDeclare.subst(iop_imm)
-        decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
-        decode_block = ROrImmDecode.subst(iop)
-        exec_output = MemExecute.subst(iop) + MemExecute.subst(iop_imm)
-        return (header_output, decoder_output, exec_output, decode_block)
-}};
-
-def format Load(code, width, *opt_flags) {{
-        (header_output,
-         decoder_output,
-         exec_output,
-         decode_block) = doMemFormat(code,
-             loadString % {"width":width}, '', name, Name, opt_flags)
-}};
-
-def format Store(code, width, *opt_flags) {{
-        (header_output,
-         decoder_output,
-         exec_output,
-         decode_block) = doMemFormat(code, '',
-             storeString % {"width":width}, name, Name, opt_flags)
-}};
-
-def format LoadStore(code, width, *opt_flags) {{
-        (header_output,
-         decoder_output,
-         exec_output,
-         decode_block) = doMemFormat(code,
-             loadString % {"width":width}, storeString % {"width":width},
-             name, Name, opt_flags)
-}};
diff --git a/arch/sparc/isa/formats/nop.isa b/arch/sparc/isa/formats/nop.isa
deleted file mode 100644
index df7503eee..000000000
--- a/arch/sparc/isa/formats/nop.isa
+++ /dev/null
@@ -1,62 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Nop instruction
-//
-
-output header {{
-        /**
-         * Nop class.
-         */
-        class Nop : public SparcStaticInst
-        {
-          public:
-            // Constructor
-            Nop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
-                SparcStaticInst(mnem, _machInst, __opClass)
-            {
-            }
-
-            // All Nop instructions do the same thing, so this can be
-            // defined here. Nops can be defined directly, so there needs
-            // to be a default implementation
-            Fault execute(%(CPU_exec_context)s *xc,
-                Trace::InstRecord *traceData) const
-            {
-                //Nothing to see here, move along
-                return NoFault;
-            }
-
-            std::string generateDisassembly(Addr pc,
-                    const SymbolTable *symtab) const;
-        };
-}};
-
-output decoder {{
-        std::string Nop::generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
-        {
-            std::stringstream response;
-            printMnemonic(response, mnemonic);
-            return response.str();
-        }
-}};
-
-def template NopExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
-                Trace::InstRecord *traceData) const
-        {
-            //Nothing to see here, move along
-            return NoFault;
-        }
-}};
-
-// Primary format for integer operate instructions:
-def format Nop(code, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'Nop', cblk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecode.subst(iop)
-        exec_output = NopExecute.subst(iop)
-}};
diff --git a/arch/sparc/isa/formats/priv.isa b/arch/sparc/isa/formats/priv.isa
deleted file mode 100644
index f9fea01f2..000000000
--- a/arch/sparc/isa/formats/priv.isa
+++ /dev/null
@@ -1,139 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Privilege mode instructions
-//
-
-output header {{
-        /**
-         * Base class for privelege mode operations.
-         */
-        class Priv : public SparcStaticInst
-        {
-          protected:
-            // Constructor
-            Priv(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
-                SparcStaticInst(mnem, _machInst, __opClass)
-            {
-            }
-
-            std::string generateDisassembly(Addr pc,
-                    const SymbolTable *symtab) const;
-        };
-
-        /**
-         * Base class for user mode "tick" access.
-         */
-        class PrivTick : public SparcStaticInst
-        {
-          protected:
-            // Constructor
-            PrivTick(const char *mnem, ExtMachInst _machInst,
-                    OpClass __opClass) :
-                SparcStaticInst(mnem, _machInst, __opClass)
-            {
-            }
-
-            std::string generateDisassembly(Addr pc,
-                    const SymbolTable *symtab) const;
-        };
-
-        /**
-         * Base class for privelege mode operations with immediates.
-         */
-        class PrivImm : public Priv
-        {
-          protected:
-            // Constructor
-            PrivImm(const char *mnem, ExtMachInst _machInst,
-                    OpClass __opClass) :
-                Priv(mnem, _machInst, __opClass), imm(SIMM13)
-            {
-            }
-
-            int32_t imm;
-        };
-
-        /**
-         * Base class for user mode "tick" access with immediates.
-         */
-        class PrivTickImm : public PrivTick
-        {
-          protected:
-            // Constructor
-            PrivTickImm(const char *mnem, ExtMachInst _machInst,
-                    OpClass __opClass) :
-                PrivTick(mnem, _machInst, __opClass), imm(SIMM13)
-            {
-            }
-
-            int32_t imm;
-        };
-}};
-
-output decoder {{
-        std::string Priv::generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
-        {
-                return "Privileged Instruction";
-        }
-
-        std::string PrivTick::generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
-        {
-                return "Regular access to Tick";
-        }
-}};
-
-def template PrivExecute {{
-    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
-            Trace::InstRecord *traceData) const
-    {
-        %(op_decl)s;
-        %(op_rd)s;
-
-        //If the processor isn't in privileged mode, fault out right away
-        if(%(check)s)
-            return new PrivilegedAction;
-
-        %(code)s;
-        %(op_wb)s;
-        return NoFault;
-    }
-}};
-
-let {{
-    def doPrivFormat(code, checkCode, name, Name, opt_flags):
-        (usesImm, code, immCode,
-         rString, iString) = splitOutImm(code)
-        iop = InstObjParams(name, Name, 'Priv', code,
-                opt_flags, ("check", checkCode))
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        exec_output = PrivExecute.subst(iop)
-        if usesImm:
-            imm_iop = InstObjParams(name, Name + 'Imm', 'PrivImm',
-                    immCode, opt_flags, ("check", checkCode))
-            header_output += BasicDeclare.subst(imm_iop)
-            decoder_output += BasicConstructor.subst(imm_iop)
-            exec_output += PrivExecute.subst(imm_iop)
-            decode_block = ROrImmDecode.subst(iop)
-        else:
-            decode_block = BasicDecode.subst(iop)
-        return (header_output, decoder_output, exec_output, decode_block)
-}};
-
-// Primary format for integer operate instructions:
-def format Priv(code, *opt_flags) {{
-        checkCode = "(!PstatePriv)"
-        (header_output, decoder_output,
-         exec_output, decode_block) = doPrivFormat(code,
-             checkCode, name, Name, opt_flags)
-}};
-
-// Primary format for integer operate instructions:
-def format PrivTick(code, *opt_flags) {{
-        checkCode = "(!PstatePriv && TickNpt)"
-        (header_output, decoder_output,
-         exec_output, decode_block) = doPrivFormat(code,
-             checkCode, name, Name, opt_flags)
-}};
diff --git a/arch/sparc/isa/formats/trap.isa b/arch/sparc/isa/formats/trap.isa
deleted file mode 100644
index f6a45ca48..000000000
--- a/arch/sparc/isa/formats/trap.isa
+++ /dev/null
@@ -1,64 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Trap instructions
-//
-
-output header {{
-        /**
-         * Base class for trap instructions,
-         * or instructions that always fault.
-         */
-        class Trap : public SparcStaticInst
-        {
-          protected:
-
-            // Constructor
-            Trap(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
-                SparcStaticInst(mnem, _machInst, __opClass), trapNum(SW_TRAP)
-            {
-            }
-
-            std::string generateDisassembly(Addr pc,
-                    const SymbolTable *symtab) const;
-
-            int trapNum;
-        };
-}};
-
-output decoder {{
-        std::string Trap::generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
-        {
-            std::stringstream response;
-
-            printMnemonic(response, mnemonic);
-            ccprintf(response, " ");
-            printReg(response, _srcRegIdx[0]);
-            ccprintf(response, ", 0x%x", trapNum);
-            ccprintf(response, ", or ");
-            printReg(response, _srcRegIdx[1]);
-            return response.str();
-        }
-}};
-
-def template TrapExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
-                Trace::InstRecord *traceData) const
-        {
-            Fault fault = NoFault;
-            %(op_decl)s;
-            %(op_rd)s;
-            %(code)s
-            return fault;
-        }
-}};
-
-def format Trap(code, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'Trap', cblk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecode.subst(iop)
-        exec_output = TrapExecute.subst(iop)
-}};
diff --git a/arch/sparc/isa/formats/unknown.isa b/arch/sparc/isa/formats/unknown.isa
deleted file mode 100644
index 223111905..000000000
--- a/arch/sparc/isa/formats/unknown.isa
+++ /dev/null
@@ -1,46 +0,0 @@
-////////////////////////////////////////////////////////////////////
-//
-// Unknown instructions
-//
-
-output header {{
-        /**
-         * Class for Unknown/Illegal instructions
-         */
-        class Unknown : public SparcStaticInst
-        {
-          public:
-
-            // Constructor
-            Unknown(ExtMachInst _machInst) :
-                    SparcStaticInst("unknown", _machInst, No_OpClass)
-            {
-            }
-
-            %(BasicExecDeclare)s
-
-            std::string generateDisassembly(Addr pc,
-                    const SymbolTable *symtab) const;
-
-        };
-}};
-
-output decoder {{
-        std::string Unknown::generateDisassembly(Addr pc,
-                const SymbolTable *symtab) const
-        {
-            return "Unknown instruction";
-        }
-}};
-
-output exec {{
-        Fault Unknown::execute(%(CPU_exec_context)s *xc,
-                Trace::InstRecord *traceData) const
-        {
-            return new IllegalInstruction;
-        }
-}};
-
-def format Unknown() {{
-        decode_block = 'return new Unknown(machInst);\n'
-}};