Fixes to SPARC syscall emulation mode.

arch/sparc/isa/base.isa:
    Added a set of abbreviations for the different condition tests.
arch/sparc/isa/decoder.isa:
    Fixes and additions to get syscall emulation closer to working.
arch/sparc/isa/formats/branch.isa:
    Fixed branches so that the immediate version actually uses the immediate value
arch/sparc/isa/formats/integerop.isa:
    Compute the condition codes -before- writing to the state of the machine.
arch/sparc/isa/formats/mem.isa:
    An attempt to fix up the output of the disassembly of loads and stores.
arch/sparc/isa/formats/trap.isa:
    Added code to disassemble a trap instruction. This probably needs to be fixed up so there are immediate and register versions.
arch/sparc/isa/operands.isa:
    Added an R1 operand, and fixed up the numbering
arch/sparc/isa_traits.hh:
    SyscallNumReg is no longer needed, the max number of sources and destinations are fixed up, and the syscall return uses xcc instead of icc.
arch/sparc/linux/process.cc:
arch/sparc/linux/process.hh:
    Added a getresuidFunc syscall implementation. This isn't actually used, but I thought it was and will leave it in.
arch/sparc/process.cc:
arch/sparc/process.hh:
    Fixed up how the initial stack frame is set up.
arch/sparc/regfile.hh:
    Changed the number of windows from 6 to 32 so we don't have to worry about spill and fill traps for now, and commented out the register file setting itself up.
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
cpu/simple/cpu.hh:
sim/process.cc:
sim/process.hh:
    Changed the syscall mechanism to pass down the syscall number directly.

--HG--
extra : convert_revision : 15723b949a0ddb3d24e68c079343b4dba2439f43

4 files changed, 22 insertions, 11 deletions

diff --git a/arch/sparc/isa/formats/branch.isa b/arch/sparc/isa/formats/branch.isa
index e4ce4592c..b76f7a9f6 100644
--- a/arch/sparc/isa/formats/branch.isa
+++ b/arch/sparc/isa/formats/branch.isa
@@ -230,14 +230,13 @@ def template BranchExecute {{
 def format Branch(code, *opt_flags) {{
         (usesImm, code, immCode,
          rString, iString) = splitOutImm(code)
-        codeBlk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'Branch', codeBlk, opt_flags)
+        iop = InstObjParams(name, Name, 'Branch', code, opt_flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
         exec_output = BranchExecute.subst(iop)
         if usesImm:
             imm_iop = InstObjParams(name, Name + 'Imm', 'BranchImm' + iString,
-                    codeBlk, opt_flags)
+                    immCode, opt_flags)
             header_output += BasicDeclare.subst(imm_iop)
             decoder_output += BasicConstructor.subst(imm_iop)
             exec_output += BranchExecute.subst(imm_iop)
diff --git a/arch/sparc/isa/formats/integerop.isa b/arch/sparc/isa/formats/integerop.isa
index f14f9e858..401af2e51 100644
--- a/arch/sparc/isa/formats/integerop.isa
+++ b/arch/sparc/isa/formats/integerop.isa
@@ -243,8 +243,8 @@ def template IntOpExecute {{
             //Write the resulting state to the execution context
             if(fault == NoFault)
             {
-                %(op_wb)s;
                 %(cc_code)s;
+                %(op_wb)s;
             }
             return fault;
         }
diff --git a/arch/sparc/isa/formats/mem.isa b/arch/sparc/isa/formats/mem.isa
index db2a4aaaa..e15349c7b 100644
--- a/arch/sparc/isa/formats/mem.isa
+++ b/arch/sparc/isa/formats/mem.isa
@@ -47,17 +47,18 @@ output decoder {{
         {
             std::stringstream response;
             bool load = flags[IsLoad];
+            bool save = flags[IsStore];
 
             printMnemonic(response, mnemonic);
-            if(!load)
+            if(save)
             {
                 printReg(response, _srcRegIdx[0]);
                 ccprintf(response, ", ");
             }
             ccprintf(response, "[ ");
-            printReg(response, _srcRegIdx[load ? 0 : 1]);
+            printReg(response, _srcRegIdx[!save ? 0 : 1]);
             ccprintf(response, " + ");
-            printReg(response, _srcRegIdx[load ? 1 : 2]);
+            printReg(response, _srcRegIdx[!save ? 1 : 2]);
             ccprintf(response, " ]");
             if(load)
             {
@@ -73,15 +74,16 @@ output decoder {{
         {
             std::stringstream response;
             bool load = flags[IsLoad];
+            bool save = flags[IsStore];
 
             printMnemonic(response, mnemonic);
-            if(!load)
+            if(save)
             {
                 printReg(response, _srcRegIdx[0]);
                 ccprintf(response, ", ");
             }
             ccprintf(response, "[ ");
-            printReg(response, _srcRegIdx[load ? 0 : 1]);
+            printReg(response, _srcRegIdx[!save ? 0 : 1]);
             ccprintf(response, " + 0x%x ]", imm);
             if(load)
             {
diff --git a/arch/sparc/isa/formats/trap.isa b/arch/sparc/isa/formats/trap.isa
index 5608548bd..f6a45ca48 100644
--- a/arch/sparc/isa/formats/trap.isa
+++ b/arch/sparc/isa/formats/trap.isa
@@ -14,12 +14,14 @@ output header {{
 
             // Constructor
             Trap(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
-                SparcStaticInst(mnem, _machInst, __opClass)
+                SparcStaticInst(mnem, _machInst, __opClass), trapNum(SW_TRAP)
             {
             }
 
             std::string generateDisassembly(Addr pc,
                     const SymbolTable *symtab) const;
+
+            int trapNum;
         };
 }};
 
@@ -27,7 +29,15 @@ output decoder {{
         std::string Trap::generateDisassembly(Addr pc,
                 const SymbolTable *symtab) const
         {
-            return "Trap instruction";
+            std::stringstream response;
+
+            printMnemonic(response, mnemonic);
+            ccprintf(response, " ");
+            printReg(response, _srcRegIdx[0]);
+            ccprintf(response, ", 0x%x", trapNum);
+            ccprintf(response, ", or ");
+            printReg(response, _srcRegIdx[1]);
+            return response.str();
         }
 }};