Fixed up the isa description. Also added some capability to the isa_parser in the InstObjParams constructor.

arch/isa_parser.py:
    Expanded the capability of the InstObjParams constructor to allow adding in extra keys for use in templates. These are added as key, value tuples as optional arguements.
arch/sparc/isa/base.isa:
arch/sparc/isa/formats/mem.isa:
arch/sparc/isa/formats/priv.isa:
    The genCompositeIop function is no longer needed, as this functionality is now in the InstObjParams constructor.
arch/sparc/isa/decoder.isa:
    Fixed up alot of instructions, and fixed indentation.
arch/sparc/isa/formats/integerop.isa:
    The genCompositeIop function is no longer needed, as this functionality is now in the InstObjParams constructor. Also changed the immediate values to be signed.
base/traceflags.py:
    Added SPARC traceflag
configs/test/hello_sparc:
    Recompiled without -mflat
cpu/cpu_exec_context.cc:
    Used the regfile clear function rather than memsetting to 0.

--HG--
extra : convert_revision : b9da6f264f3ebc4ce1815008dfff7f476b247ee9

3 files changed, 79 insertions, 82 deletions

diff --git a/arch/sparc/isa/formats/integerop.isa b/arch/sparc/isa/formats/integerop.isa
index 2c2123f86..f14f9e858 100644
--- a/arch/sparc/isa/formats/integerop.isa
+++ b/arch/sparc/isa/formats/integerop.isa
@@ -37,7 +37,7 @@ output header {{
             {
             }
 
-            uint32_t imm;
+            int32_t imm;
 
             std::string generateDisassembly(Addr pc,
                 const SymbolTable *symtab) const;
@@ -57,7 +57,7 @@ output header {{
                     OpClass __opClass) :
                 IntOpImm(mnem, _machInst, __opClass)
             {
-                imm = SIMM10;
+                imm = sign_ext(SIMM10, 10);
             }
         };
 
@@ -72,7 +72,7 @@ output header {{
                     OpClass __opClass) :
                 IntOpImm(mnem, _machInst, __opClass)
             {
-                imm = SIMM13;
+                imm = sign_ext(SIMM13, 13);
             }
         };
 
@@ -195,7 +195,7 @@ output decoder {{
             if(!printPseudoOps(response, pc, symtab))
             {
                 printMnemonic(response, mnemonic);
-                if (_numSrcRegs > 1)
+                if (_numSrcRegs > 0)
                 {
                     printReg(response, _srcRegIdx[0]);
                     for(int x = 1; x < _numSrcRegs - 1; x++)
@@ -254,14 +254,14 @@ let {{
     def doIntFormat(code, ccCode, name, Name, opt_flags):
         (usesImm, code, immCode,
          rString, iString) = splitOutImm(code)
-        iop = genCompositeIop(code, name, Name,
-                'IntOp', opt_flags, cc_code=ccCode)
+        iop = InstObjParams(name, Name,	'IntOp', code,
+                opt_flags, ("cc_code", ccCode))
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
         exec_output = IntOpExecute.subst(iop)
         if usesImm:
-            imm_iop = genCompositeIop(code, name, Name + 'Imm',
-                    'IntOpImm' + iString, opt_flags, cc_code=ccCode)
+            imm_iop = InstObjParams(name, Name + 'Imm', 'IntOpImm' + iString,
+                    immCode, opt_flags, ("cc_code", ccCode))
             header_output += BasicDeclare.subst(imm_iop)
             decoder_output += BasicConstructor.subst(imm_iop)
             exec_output += IntOpExecute.subst(imm_iop)
@@ -316,8 +316,8 @@ def format IntOpCcRes(code, *opt_flags) {{
 }};
 
 def format SetHi(code, *opt_flags) {{
-    iop = genCompositeIop(code, name, Name, 'SetHi',
-            opt_flags, cc_code='')
+    iop = InstObjParams(name, Name, 'SetHi',
+            code, opt_flags, ("cc_code", ''))
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
     exec_output = IntOpExecute.subst(iop)
diff --git a/arch/sparc/isa/formats/mem.isa b/arch/sparc/isa/formats/mem.isa
index 8c9d21c01..db2a4aaaa 100644
--- a/arch/sparc/isa/formats/mem.isa
+++ b/arch/sparc/isa/formats/mem.isa
@@ -37,7 +37,7 @@ output header {{
             std::string generateDisassembly(Addr pc,
                     const SymbolTable *symtab) const;
 
-            int imm;
+            int32_t imm;
         };
 }};
 
@@ -46,7 +46,7 @@ output decoder {{
                 const SymbolTable *symtab) const
         {
             std::stringstream response;
-            bool load = (_numDestRegs == 1);
+            bool load = flags[IsLoad];
 
             printMnemonic(response, mnemonic);
             if(!load)
@@ -72,7 +72,7 @@ output decoder {{
                 const SymbolTable *symtab) const
         {
             std::stringstream response;
-            bool load = (_numDestRegs == 1);
+            bool load = flags[IsLoad];
 
             printMnemonic(response, mnemonic);
             if(!load)
@@ -102,7 +102,9 @@ def template MemExecute {{
             %(op_decl)s;
             %(op_rd)s;
             %(ea_code)s;
+            %(load)s;
             %(code)s;
+            %(store)s;
 
             if(fault == NoFault)
             {
@@ -114,16 +116,49 @@ def template MemExecute {{
         }
 }};
 
-// Primary format for memory instructions:
-def format Mem(code, *opt_flags) {{
+let {{
+    # Leave memAccessFlags at 0 for now
+    loadString = "xc->read(EA, (uint%(width)s_t&)Mem, 0);"
+    storeString = "uint64_t write_result = 0; \
+    xc->write((uint%(width)s_t)Mem, EA, 0, &write_result);"
+
+    def doMemFormat(code, load, store, name, Name, opt_flags):
         addrCalcReg = 'EA = Rs1 + Rs2;'
         addrCalcImm = 'EA = Rs1 + SIMM13;'
-        iop = genCompositeIop(code, name, Name, 'Mem',
-                opt_flags, ea_code=addrCalcReg)
-        iop_imm = genCompositeIop(code, name, Name + 'Imm', 'MemImm',
-                opt_flags, ea_code=addrCalcImm)
+        iop = InstObjParams(name, Name, 'Mem', code,
+                opt_flags, ("ea_code", addrCalcReg),
+                ("load", load), ("store", store))
+        iop_imm = InstObjParams(name, Name + 'Imm', 'MemImm', code,
+                opt_flags, ("ea_code", addrCalcImm),
+                ("load", load), ("store", store))
         header_output = BasicDeclare.subst(iop) + BasicDeclare.subst(iop_imm)
         decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
         decode_block = ROrImmDecode.subst(iop)
         exec_output = MemExecute.subst(iop) + MemExecute.subst(iop_imm)
+        return (header_output, decoder_output, exec_output, decode_block)
+}};
+
+def format Load(code, width, *opt_flags) {{
+        (header_output,
+         decoder_output,
+         exec_output,
+         decode_block) = doMemFormat(code,
+             loadString % {"width":width}, '', name, Name, opt_flags)
+}};
+
+def format Store(code, width, *opt_flags) {{
+        (header_output,
+         decoder_output,
+         exec_output,
+         decode_block) = doMemFormat(code, '',
+             storeString % {"width":width}, name, Name, opt_flags)
+}};
+
+def format LoadStore(code, width, *opt_flags) {{
+        (header_output,
+         decoder_output,
+         exec_output,
+         decode_block) = doMemFormat(code,
+             loadString % {"width":width}, storeString % {"width":width},
+             name, Name, opt_flags)
 }};
diff --git a/arch/sparc/isa/formats/priv.isa b/arch/sparc/isa/formats/priv.isa
index 162ad5ee0..f9fea01f2 100644
--- a/arch/sparc/isa/formats/priv.isa
+++ b/arch/sparc/isa/formats/priv.isa
@@ -50,7 +50,7 @@ output header {{
             {
             }
 
-            uint32_t imm;
+            int32_t imm;
         };
 
         /**
@@ -66,7 +66,7 @@ output header {{
             {
             }
 
-            uint32_t imm;
+            int32_t imm;
         };
 }};
 
@@ -91,35 +91,8 @@ def template PrivExecute {{
         %(op_decl)s;
         %(op_rd)s;
 
-        //Since these are processed inside templates and not in codeblocks,
-        //They aren't translated by the isa_parser. Their names begin with
-        //underscores so they don't cause conflicts.
-        uint32_t _PstatePriv = xc->readMiscReg(MISCREG_PSTATE_PRIV);
-
         //If the processor isn't in privileged mode, fault out right away
-        if(!_PstatePriv)
-            return new PrivilegedOpcode;
-
-        %(code)s;
-        %(op_wb)s;
-        return NoFault;
-    }
-}};
-
-def template PrivTickExecute {{
-    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
-            Trace::InstRecord *traceData) const
-    {
-        %(op_decl)s;
-        %(op_rd)s;
-
-        //Since these are processed inside templates and not in codeblocks,
-        //They aren't translated by the isa_parser. Their names begin with
-        //underscores so they don't cause conflicts.
-        uint32_t _PstatePriv = xc->readMiscReg(MISCREG_PSTATE_PRIV);
-        uint32_t _TickNpt = xc->readMiscReg(MISCREG_TICK_NPT);
-        //If the processor isn't in privileged mode, fault out right away
-        if(!_PstatePriv && _TickNpt)
+        if(%(check)s)
             return new PrivilegedAction;
 
         %(code)s;
@@ -128,50 +101,39 @@ def template PrivTickExecute {{
     }
 }};
 
-// Primary format for integer operate instructions:
-def format Priv(code, *opt_flags) {{
-        uses_imm = (code.find('Rs2_or_imm13') != -1)
-        if uses_imm:
-            orig_code = code
-            code = re.sub(r'Rs2_or_imm13', 'Rs2', orig_code)
-            imm_code = re.sub(r'Rs2_or_imm13(\.\w+)?', 'imm', orig_code)
-        cblk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'Priv', cblk, opt_flags)
+let {{
+    def doPrivFormat(code, checkCode, name, Name, opt_flags):
+        (usesImm, code, immCode,
+         rString, iString) = splitOutImm(code)
+        iop = InstObjParams(name, Name, 'Priv', code,
+                opt_flags, ("check", checkCode))
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
         exec_output = PrivExecute.subst(iop)
-        if uses_imm:
-            imm_cblk = CodeBlock(imm_code)
-            imm_iop = InstObjParams(name, Name + 'Imm', 'PrivImm', imm_cblk,
-                                    opt_flags)
+        if usesImm:
+            imm_iop = InstObjParams(name, Name + 'Imm', 'PrivImm',
+                    immCode, opt_flags, ("check", checkCode))
             header_output += BasicDeclare.subst(imm_iop)
             decoder_output += BasicConstructor.subst(imm_iop)
             exec_output += PrivExecute.subst(imm_iop)
             decode_block = ROrImmDecode.subst(iop)
         else:
             decode_block = BasicDecode.subst(iop)
+        return (header_output, decoder_output, exec_output, decode_block)
+}};
+
+// Primary format for integer operate instructions:
+def format Priv(code, *opt_flags) {{
+        checkCode = "(!PstatePriv)"
+        (header_output, decoder_output,
+         exec_output, decode_block) = doPrivFormat(code,
+             checkCode, name, Name, opt_flags)
 }};
 
 // Primary format for integer operate instructions:
 def format PrivTick(code, *opt_flags) {{
-        uses_imm = (code.find('Rs2_or_imm13') != -1)
-        if uses_imm:
-            orig_code = code
-            code = re.sub(r'Rs2_or_imm13', 'Rs2', orig_code)
-            imm_code = re.sub(r'Rs2_or_imm13(\.\w+)?', 'imm', orig_code)
-        cblk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'PrivTick', cblk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        exec_output = PrivTickExecute.subst(iop)
-        if uses_imm:
-            imm_cblk = CodeBlock(imm_code)
-            imm_iop = InstObjParams(name, Name + 'Imm', 'PrivTickImm', imm_cblk,
-                                    opt_flags)
-            header_output += BasicDeclare.subst(imm_iop)
-            decoder_output += BasicConstructor.subst(imm_iop)
-            exec_output += PrivTickExecute.subst(imm_iop)
-            decode_block = Rb2OrImmDecode.subst(iop)
-        else:
-            decode_block = BasicDecode.subst(iop)
+        checkCode = "(!PstatePriv && TickNpt)"
+        (header_output, decoder_output,
+         exec_output, decode_block) = doPrivFormat(code,
+             checkCode, name, Name, opt_flags)
 }};