Merge m5.eecs.umich.edu:/bk/newmem

into  ewok.(none):/home/gblack/m5/newmem

cpu/simple/cpu.cc:
    Hand merged

--HG--
extra : convert_revision : 68414730c23d41c30cfb7bcfa604029a5fc8622c

3 files changed, 35 insertions, 5 deletions

diff --git a/arch/sparc/isa/formats/branch.isa b/arch/sparc/isa/formats/branch.isa
index b76f7a9f6..37bdb9402 100644
--- a/arch/sparc/isa/formats/branch.isa
+++ b/arch/sparc/isa/formats/branch.isa
@@ -194,7 +194,7 @@ output decoder {{
             {
                 ccprintf(response, " <%s", symbol);
                 if(symbolAddr != target)
-                    ccprintf(response, "+0x%x>", target - symbolAddr);
+                    ccprintf(response, "+%d>", target - symbolAddr);
                 else
                     ccprintf(response, ">");
             }
@@ -226,8 +226,25 @@ def template BranchExecute {{
         }
 }};
 
+let {{
+    handle_annul = '''
+    {
+        if(A)
+        {
+            NPC = xc->readNextNPC();
+            NNPC = NPC + 4;
+        }
+        else
+        {
+            NPC = xc->readNextPC();
+            NNPC = xc->readNextNPC();
+        }
+    }'''
+}};
+
 // Primary format for branch instructions:
 def format Branch(code, *opt_flags) {{
+        code = re.sub(r'handle_annul', handle_annul, code)
         (usesImm, code, immCode,
          rString, iString) = splitOutImm(code)
         iop = InstObjParams(name, Name, 'Branch', code, opt_flags)
@@ -247,6 +264,7 @@ def format Branch(code, *opt_flags) {{
 
 // Primary format for branch instructions:
 def format Branch19(code, *opt_flags) {{
+        code = re.sub(r'handle_annul', handle_annul, code)
         codeBlk = CodeBlock(code)
         iop = InstObjParams(name, Name, 'Branch19', codeBlk, opt_flags)
         header_output = BasicDeclare.subst(iop)
@@ -257,6 +275,7 @@ def format Branch19(code, *opt_flags) {{
 
 // Primary format for branch instructions:
 def format Branch22(code, *opt_flags) {{
+        code = re.sub(r'handle_annul', handle_annul, code)
         codeBlk = CodeBlock(code)
         iop = InstObjParams(name, Name, 'Branch22', codeBlk, opt_flags)
         header_output = BasicDeclare.subst(iop)
@@ -267,6 +286,7 @@ def format Branch22(code, *opt_flags) {{
 
 // Primary format for branch instructions:
 def format Branch30(code, *opt_flags) {{
+        code = re.sub(r'handle_annul', handle_annul, code)
         codeBlk = CodeBlock(code)
         iop = InstObjParams(name, Name, 'Branch30', codeBlk, opt_flags)
         header_output = BasicDeclare.subst(iop)
@@ -277,6 +297,7 @@ def format Branch30(code, *opt_flags) {{
 
 // Primary format for branch instructions:
 def format BranchSplit(code, *opt_flags) {{
+        code = re.sub(r'handle_annul', handle_annul, code)
         codeBlk = CodeBlock(code)
         iop = InstObjParams(name, Name, 'BranchSplit', codeBlk, opt_flags)
         header_output = BasicDeclare.subst(iop)
diff --git a/arch/sparc/isa/formats/integerop.isa b/arch/sparc/isa/formats/integerop.isa
index 401af2e51..407a3e3cd 100644
--- a/arch/sparc/isa/formats/integerop.isa
+++ b/arch/sparc/isa/formats/integerop.isa
@@ -271,14 +271,22 @@ let {{
         return (header_output, decoder_output, exec_output, decode_block)
 
     calcCcCode = '''
-        CcrIccN = (Rd >> 63) & 1;
-        CcrIccZ = (Rd == 0);
-        CcrXccN = (Rd >> 31) & 1;
-        CcrXccZ = ((Rd & 0xFFFFFFFF) == 0);
+        CcrIccN = (Rd >> 31) & 1;
+        CcrIccZ = ((Rd & 0xFFFFFFFF) == 0);
+        CcrXccN = (Rd >> 63) & 1;
+        CcrXccZ = (Rd == 0);
         CcrIccV = %(ivValue)s;
         CcrIccC = %(icValue)s;
         CcrXccV = %(xvValue)s;
         CcrXccC = %(xcValue)s;
+        DPRINTF(Sparc, "in = %%d\\n", CcrIccN);
+        DPRINTF(Sparc, "iz = %%d\\n", CcrIccZ);
+        DPRINTF(Sparc, "xn = %%d\\n", CcrXccN);
+        DPRINTF(Sparc, "xz = %%d\\n", CcrXccZ);
+        DPRINTF(Sparc, "iv = %%d\\n", CcrIccV);
+        DPRINTF(Sparc, "ic = %%d\\n", CcrIccC);
+        DPRINTF(Sparc, "xv = %%d\\n", CcrXccV);
+        DPRINTF(Sparc, "xc = %%d\\n", CcrXccC);
         '''
 }};
 
diff --git a/arch/sparc/isa/formats/mem.isa b/arch/sparc/isa/formats/mem.isa
index e15349c7b..ab8b85a94 100644
--- a/arch/sparc/isa/formats/mem.isa
+++ b/arch/sparc/isa/formats/mem.isa
@@ -104,6 +104,7 @@ def template MemExecute {{
             %(op_decl)s;
             %(op_rd)s;
             %(ea_code)s;
+            DPRINTF(Sparc, "The address is 0x%x\n", EA);
             %(load)s;
             %(code)s;
             %(store)s;