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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-03-28 19:36:34 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-03-28 19:36:34 -0500 |
| commit | 818f3ae22f324601742801b166350691cddf3a2a (patch) | |
| tree | b3b6f7fa63b2908371e20f943e94b50d7de1b33c /arch/sparc/isa/operands.isa | |
| parent | 1507bfb20a4053abb9f8eb1a97bafc800a9c934f (diff) | |
| download | gem5-818f3ae22f324601742801b166350691cddf3a2a.tar.xz | |
SPARC compiles for SE!
arch/sparc/isa/decoder.isa:
Replaced register number munging with RdLow and RdHigh operands.
arch/sparc/isa/formats/mem.isa:
Fixed how the address calculation code is dealt with.
arch/sparc/isa/operands.isa:
Changed the tabbing so that the whole oeprands block was consistent, and added RdLow and RdHigh operands. These registers are used when Rd is meant to refer to a pair of registers, rather than just one.
arch/sparc/isa_traits.hh:
Moved some functions to the new (to SPARC) utility.hh file. Also, dummy Fpcr_DepTag and Uniq_DepTag DepTags were added to pacify Tru64. These need to be removed, and Tru64 needs to not be compiled in if it isn't appropriate.
arch/sparc/regfile.hh:
Changed regSpace to have the correct size.
arch/sparc/utility.hh:
A new file for sparc to match the one for alpha.
--HG--
extra : convert_revision : ff6b529093d15f327ec11f067ad533bacdba9932
Diffstat (limited to 'arch/sparc/isa/operands.isa')
| -rw-r--r-- | arch/sparc/isa/operands.isa | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/arch/sparc/isa/operands.isa b/arch/sparc/isa/operands.isa index abfdf7bcd..0d521fae0 100644 --- a/arch/sparc/isa/operands.isa +++ b/arch/sparc/isa/operands.isa @@ -16,18 +16,20 @@ def operands {{ # Int regs default to unsigned, but code should not count on this. # For clarity, descriptions that depend on unsigned behavior should # explicitly specify '.uq'. - 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), - 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 2), - 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 3), + 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1), + 'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2), + 'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3), + 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4), + 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5), #'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1), #'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2), #'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3), - 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), + 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4), #'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4), #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1), - 'R0': ('IntReg', 'udw', '0', None, 1), - 'R16': ('IntReg', 'udw', '16', None, 1), + 'R0': ('IntReg', 'udw', '0', None, 1), + 'R16': ('IntReg', 'udw', '16', None, 1), # Control registers 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1), 'PstateAg': ('ControlReg', 'udw', 'MISCREG_PSTATE_AG', None, 2), |