diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2006-04-18 09:44:45 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-04-18 09:44:45 -0400 |
| commit | cae6b571d63b38c3177f5b47891021ba69386453 (patch) | |
| tree | 6039a7ce3381b6c5448fc127bdb7b063ae52115e /arch/sparc/isa/operands.isa | |
| parent | 0534e355b77497a1272f6078edae1692d87a15cf (diff) | |
| parent | 609c4ecea618c6406e50432e38882925db7b7ede (diff) | |
| download | gem5-cae6b571d63b38c3177f5b47891021ba69386453.tar.xz | |
Merge m5.eecs.umich.edu:/bk/newmem
into ewok.(none):/home/gblack/m5/newmem
--HG--
extra : convert_revision : 3eb97976caf57e43119a998c31128ca6f163c05b
Diffstat (limited to 'arch/sparc/isa/operands.isa')
| -rw-r--r-- | arch/sparc/isa/operands.isa | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/sparc/isa/operands.isa b/arch/sparc/isa/operands.isa index 17e58ad59..64a032eea 100644 --- a/arch/sparc/isa/operands.isa +++ b/arch/sparc/isa/operands.isa @@ -30,8 +30,9 @@ def operands {{ #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1), #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1), 'R0': ('IntReg', 'udw', '0', None, 6), - 'R15': ('IntReg', 'udw', '15', 'IsInteger', 7), - 'R16': ('IntReg', 'udw', '16', None, 8), + 'R1': ('IntReg', 'udw', '1', None, 7), + 'R15': ('IntReg', 'udw', '15', 'IsInteger', 8), + 'R16': ('IntReg', 'udw', '16', None, 9), # Control registers 'Pstate': ('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1), 'PstateAg': ('ControlReg', 'udw', 'MISCREG_PSTATE_AG', None, 2), |