summaryrefslogtreecommitdiff
path: root/arch/sparc/isa/operands.isa
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2006-03-07 04:33:10 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-03-07 04:33:10 -0500
commit9e43f70ac2ad7e7283a449fabafc03a5daac7029 (patch)
treedda6f0ecef8150501aa4aaddd763f334eadef6df /arch/sparc/isa/operands.isa
parentd4b246b3e9b78a77f021c6c155313abb28fa2cb9 (diff)
downloadgem5-9e43f70ac2ad7e7283a449fabafc03a5daac7029.tar.xz
Clean up of the SPARC isa description.
--HG-- extra : convert_revision : 21fe35fe4719f487168c89dd7bfc87dc38af0267
Diffstat (limited to 'arch/sparc/isa/operands.isa')
-rw-r--r--arch/sparc/isa/operands.isa7
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/sparc/isa/operands.isa b/arch/sparc/isa/operands.isa
index c5ba263d6..64f5abd08 100644
--- a/arch/sparc/isa/operands.isa
+++ b/arch/sparc/isa/operands.isa
@@ -22,11 +22,10 @@ def operands {{
#'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
#'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
#'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
- 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4)
+ 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
#'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
#'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
#'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
- # The next two are hacks for non-full-system call-pal emulation
- #'R0': ('IntReg', 'uq', '0', None, 1),
- #'R16': ('IntReg', 'uq', '16', None, 1)
+ 'R0': ('IntReg', 'udw', '0', None, 1),
+ 'R16': ('IntReg', 'udw', '16', None, 1)
}};