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authorGabe Black <gblack@eecs.umich.edu>2006-02-09 13:56:24 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-02-09 13:56:24 -0500
commit7d9b93d825dccbb9eb09e76478552a5211c9b70e (patch)
tree34c3711493803a0fee982c3ae013bed21596269b /arch/sparc/isa/operands.isa
parenta0f65246bfac279130aa67851f9c4d5c27e967b1 (diff)
downloadgem5-7d9b93d825dccbb9eb09e76478552a5211c9b70e.tar.xz
Changed the filenames to the new standard again
arch/sparc/isa/formats.isa: Changed the file extensions to .isa again. arch/sparc/isa/main.isa: Changed the file extensions to .isa again --HG-- rename : arch/sparc/isa_desc/base.h => arch/sparc/isa/base.isa rename : arch/sparc/isa_desc/bitfields.h => arch/sparc/isa/bitfields.isa rename : arch/sparc/isa_desc/decoder.h => arch/sparc/isa/decoder.isa rename : arch/sparc/isa_desc/formats.h => arch/sparc/isa/formats.isa rename : arch/sparc/isa_desc/formats/basic.format => arch/sparc/isa/formats/basic.isa rename : arch/sparc/isa_desc/formats/branch.format => arch/sparc/isa/formats/branch.isa rename : arch/sparc/isa_desc/formats/integerop.format => arch/sparc/isa/formats/integerop.isa rename : arch/sparc/isa_desc/formats/mem.format => arch/sparc/isa/formats/mem.isa rename : arch/sparc/isa_desc/formats/noop.format => arch/sparc/isa/formats/noop.isa rename : arch/sparc/isa_desc/formats/trap.format => arch/sparc/isa/formats/trap.isa rename : arch/sparc/isa_desc/includes.h => arch/sparc/isa/includes.isa rename : arch/sparc/isa_desc/isa_desc => arch/sparc/isa/main.isa rename : arch/sparc/isa_desc/operands.h => arch/sparc/isa/operands.isa extra : convert_revision : acb087e81d06ca5d67fe9b402423d7930f6ae798
Diffstat (limited to 'arch/sparc/isa/operands.isa')
-rw-r--r--arch/sparc/isa/operands.isa33
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/sparc/isa/operands.isa b/arch/sparc/isa/operands.isa
new file mode 100644
index 000000000..77de6c9c4
--- /dev/null
+++ b/arch/sparc/isa/operands.isa
@@ -0,0 +1,33 @@
+def operand_types {{
+ 'sb' : ('signed int', 8),
+ 'ub' : ('unsigned int', 8),
+ 'shw' : ('signed int', 16),
+ 'uhw' : ('unsigned int', 16),
+ 'sw' : ('signed int', 32),
+ 'uw' : ('unsigned int', 32),
+ 'sdw' : ('signed int', 64),
+ 'udw' : ('unsigned int', 64),
+ 'sf' : ('float', 32),
+ 'df' : ('float', 64),
+ 'qf' : ('float', 128)
+}};
+
+def operands {{
+ # Int regs default to unsigned, but code should not count on this.
+ # For clarity, descriptions that depend on unsigned behavior should
+ # explicitly specify '.uq'.
+ 'Rd': IntRegOperandTraits('udw', 'RD', 'IsInteger', 1),
+ 'Rs1': IntRegOperandTraits('udw', 'RS1', 'IsInteger', 2),
+ 'Rs2': IntRegOperandTraits('udw', 'RS2', 'IsInteger', 3),
+ #'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1),
+ #'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2),
+ #'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3),
+ 'Mem': MemOperandTraits('udw', None,
+ ('IsMemRef', 'IsLoad', 'IsStore'), 4)
+ #'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4),
+ #'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1),
+ #'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1),
+ # The next two are hacks for non-full-system call-pal emulation
+ #'R0': IntRegOperandTraits('uq', '0', None, 1),
+ #'R16': IntRegOperandTraits('uq', '16', None, 1)
+}};