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authorGabe Black <gblack@eecs.umich.edu>2006-02-12 11:38:26 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-02-12 11:38:26 -0500
commit94590a4dba6712ae61bfed260d7933b58b78c449 (patch)
treecbde4c0a95ab6e064649ec9ffd474a43fdd9b24e /arch/sparc/isa/operands.isa
parentb0700182662df6050c5baf46ea6bae2835b55a78 (diff)
parent79613686f0f6a8725e88e935a7c9ff4ede4cfc2b (diff)
downloadgem5-94590a4dba6712ae61bfed260d7933b58b78c449.tar.xz
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch --HG-- extra : convert_revision : 427b5c957f91e66271444acebc01e1a861790363
Diffstat (limited to 'arch/sparc/isa/operands.isa')
-rw-r--r--arch/sparc/isa/operands.isa25
1 files changed, 12 insertions, 13 deletions
diff --git a/arch/sparc/isa/operands.isa b/arch/sparc/isa/operands.isa
index 77de6c9c4..c5ba263d6 100644
--- a/arch/sparc/isa/operands.isa
+++ b/arch/sparc/isa/operands.isa
@@ -16,18 +16,17 @@ def operands {{
# Int regs default to unsigned, but code should not count on this.
# For clarity, descriptions that depend on unsigned behavior should
# explicitly specify '.uq'.
- 'Rd': IntRegOperandTraits('udw', 'RD', 'IsInteger', 1),
- 'Rs1': IntRegOperandTraits('udw', 'RS1', 'IsInteger', 2),
- 'Rs2': IntRegOperandTraits('udw', 'RS2', 'IsInteger', 3),
- #'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1),
- #'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2),
- #'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3),
- 'Mem': MemOperandTraits('udw', None,
- ('IsMemRef', 'IsLoad', 'IsStore'), 4)
- #'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4),
- #'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1),
- #'FPCR': ControlRegOperandTraits('uq', 'Fpcr', None, 1),
+ 'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
+ 'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 2),
+ 'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 3),
+ #'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
+ #'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
+ #'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
+ 'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4)
+ #'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
+ #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
+ #'FPCR': ('ControlReg', 'uq', 'Fpcr', None, 1),
# The next two are hacks for non-full-system call-pal emulation
- #'R0': IntRegOperandTraits('uq', '0', None, 1),
- #'R16': IntRegOperandTraits('uq', '16', None, 1)
+ #'R0': ('IntReg', 'uq', '0', None, 1),
+ #'R16': ('IntReg', 'uq', '16', None, 1)
}};