Changed the filenames to the new standard again

arch/sparc/isa/formats.isa:
    Changed the file extensions to .isa again.
arch/sparc/isa/main.isa:
    Changed the file extensions to .isa again

--HG--
rename : arch/sparc/isa_desc/base.h => arch/sparc/isa/base.isa
rename : arch/sparc/isa_desc/bitfields.h => arch/sparc/isa/bitfields.isa
rename : arch/sparc/isa_desc/decoder.h => arch/sparc/isa/decoder.isa
rename : arch/sparc/isa_desc/formats.h => arch/sparc/isa/formats.isa
rename : arch/sparc/isa_desc/formats/basic.format => arch/sparc/isa/formats/basic.isa
rename : arch/sparc/isa_desc/formats/branch.format => arch/sparc/isa/formats/branch.isa
rename : arch/sparc/isa_desc/formats/integerop.format => arch/sparc/isa/formats/integerop.isa
rename : arch/sparc/isa_desc/formats/mem.format => arch/sparc/isa/formats/mem.isa
rename : arch/sparc/isa_desc/formats/noop.format => arch/sparc/isa/formats/noop.isa
rename : arch/sparc/isa_desc/formats/trap.format => arch/sparc/isa/formats/trap.isa
rename : arch/sparc/isa_desc/includes.h => arch/sparc/isa/includes.isa
rename : arch/sparc/isa_desc/isa_desc => arch/sparc/isa/main.isa
rename : arch/sparc/isa_desc/operands.h => arch/sparc/isa/operands.isa
extra : convert_revision : acb087e81d06ca5d67fe9b402423d7930f6ae798

13 files changed, 1333 insertions, 0 deletions

diff --git a/arch/sparc/isa/base.isa b/arch/sparc/isa/base.isa
new file mode 100644
index 000000000..b504f1906
--- /dev/null
+++ b/arch/sparc/isa/base.isa
@@ -0,0 +1,82 @@
+////////////////////////////////////////////////////////////////////
+//
+// Base class for sparc instructions, and some support functions
+//
+
+output header {{
+        /**
+         * Base class for all SPARC static instructions.
+         */
+        class SparcStaticInst : public StaticInst<SPARCISA>
+        {
+        protected:
+
+                // Constructor.
+                SparcStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
+                    : StaticInst<SPARCISA>(mnem, _machInst, __opClass)
+                {
+                }
+
+                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        };
+
+        bool passesCondition(struct {uint8_t c:1; uint8_t v:1; uint8_t z:1; uint8_t n:1} codes, uint8_t condition);
+}};
+
+output decoder {{
+
+        std::string SparcStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+                std::stringstream ss;
+
+                ccprintf(ss, "%-10s ", mnemonic);
+
+                // just print the first two source regs... if there's
+                // a third one, it's a read-modify-write dest (Rc),
+                // e.g. for CMOVxx
+                if(_numSrcRegs > 0)
+                {
+                        printReg(ss, _srcRegIdx[0]);
+                }
+                if(_numSrcRegs > 1)
+                {
+                        ss << ",";
+                        printReg(ss, _srcRegIdx[1]);
+                }
+
+                // just print the first dest... if there's a second one,
+                // it's generally implicit
+                if(_numDestRegs > 0)
+                {
+                        if(_numSrcRegs > 0)
+                                ss << ",";
+                        printReg(ss, _destRegIdx[0]);
+                }
+
+                return ss.str();
+        }
+
+        bool passesCondition(struct {uint8_t c:1; uint8_t v:1; uint8_t z:1; uint8_t n:1} codes, uint8_t condition)
+        {
+                switch(condition)
+                {
+                        case 0b1000: return true;
+                        case 0b0000: return false;
+                        case 0b1001: return !codes.z;
+                        case 0b0001: return codes.z;
+                        case 0b1010: return !(codes.z | (codes.n ^ codes.v));
+                        case 0b0010: return codes.z | (codes.n ^ codes.v);
+                        case 0b1011: return !(codes.n ^ codes.v);
+                        case 0b0011: return (codes.n ^ codes.v);
+                        case 0b1100: return !(codes.c | codes.z);
+                        case 0b0100: return (codes.c | codes.z);
+                        case 0b1101: return !codes.c;
+                        case 0b0101: return codes.c;
+                        case 0b1110: return !codes.n;
+                        case 0b0110: return codes.n;
+                        case 0b1111: return !codes.v;
+                        case 0b0111: return codes.v;
+                }
+        }
+}};
+
diff --git a/arch/sparc/isa/bitfields.isa b/arch/sparc/isa/bitfields.isa
new file mode 100644
index 000000000..b0ac57575
--- /dev/null
+++ b/arch/sparc/isa/bitfields.isa
@@ -0,0 +1,50 @@
+////////////////////////////////////////////////////////////////////
+//
+// Bitfield definitions.
+//
+
+// Bitfields are shared liberally between instruction formats, so they are
+// simply defined alphabetically
+
+def bitfield A		<29>;
+def bitfield CC02	<20>;
+def bitfield CC03	<25>;
+def bitfield CC04	<11>;
+def bitfield CC12	<21>;
+def bitfield CC13	<26>;
+def bitfield CC14	<12>;
+def bitfield CC2	<18>;
+def bitfield CMASK	<6:4>;
+def bitfield COND2	<28:25>;
+def bitfield COND4	<17:14>;
+def bitfield D16HI	<21:20>;
+def bitfield D16LO	<13:0>;
+def bitfield DISP19	<18:0>;
+def bitfield DISP22	<21:0>;
+def bitfield DISP30	<29:0>;
+def bitfield FCN	<29:26>;
+def bitfield I		<13>;
+def bitfield IMM_ASI	<12:5>;
+def bitfield IMM22	<21:0>;
+def bitfield MMASK	<3:0>;
+def bitfield OP		<31:30>;
+def bitfield OP2	<24:22>;
+def bitfield OP3	<24:19>;
+def bitfield OPF	<13:5>;
+def bitfield OPF_CC	<13:11>;
+def bitfield OPF_LOW5	<9:5>;
+def bitfield OPF_LOW6	<10:5>;
+def bitfield P		<19>;
+def bitfield RCOND2	<27:25>;
+def bitfield RCOND3	<12:10>;
+def bitfield RCOND4	<12:10>;
+def bitfield RD		<29:25>;
+def bitfield RS1	<18:14>;
+def bitfield RS2	<4:0>;
+def bitfield SHCNT32	<4:0>;
+def bitfield SHCNT64	<5:0>;
+def bitfield SIMM10	<9:0>;
+def bitfield SIMM11	<10:0>;
+def bitfield SIMM13	<12:0>;
+def bitfield SW_TRAP	<6:0>;
+def bitfield X		<12>;
diff --git a/arch/sparc/isa/decoder.isa b/arch/sparc/isa/decoder.isa
new file mode 100644
index 000000000..06834ecc3
--- /dev/null
+++ b/arch/sparc/isa/decoder.isa
@@ -0,0 +1,638 @@
+////////////////////////////////////////////////////////////////////
+//
+// The actual decoder specification
+//
+
+decode OP default Trap::unknown({{illegal_instruction}}) {
+
+        0x0: decode OP2 {
+                0x0: Trap::illtrap({{illegal_instruction}});  //ILLTRAP
+                0x1: Branch::bpcc({{
+                        switch((CC12 << 1) | CC02)
+                        {
+                                case 1: case 3:
+                                        throw illegal_instruction;
+                                case 0:
+                                        if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND2))
+                                                ;//branchHere
+                                break;
+                                case 2:
+                                        if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, COND2))
+                                                ;//branchHere
+                                break;
+                        }
+                }});//BPcc
+                0x2: Branch::bicc({{
+                        if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND2))
+                                ;//branchHere
+                }});//Bicc
+                0x3: Branch::bpr({{
+                        switch(RCOND)
+                        {
+                                case 0: case 4:
+                                        throw illegal_instruction;
+                                case 1:
+                                        if(Rs1 == 0) ;//branchHere
+                                break;
+                                case 2:
+                                        if(Rs1 <= 0) ;//branchHere
+                                break;
+                                case 3:
+                                        if(Rs1 < 0) ;//branchHere
+                                break;
+                                case 5:
+                                        if(Rs1 != 0) ;//branchHere
+                                break;
+                                case 6:
+                                        if(Rs1 > 0) ;//branchHere
+                                break;
+                                case 7:
+                                        if(Rs1 >= 0) ;//branchHere
+                                break;
+                        }
+                }});    //BPr
+                0x4: IntegerOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}});   //SETHI (or NOP if rd == 0 and imm == 0)
+                0x5: Trap::fbpfcc({{throw fp_disabled;}}); //FBPfcc
+                0x6: Trap::fbfcc({{throw fp_disabled;}});  //FBfcc
+        }
+        0x1: Branch::call({{
+                //branch here
+                Rd = xc->pc;
+        }});
+        0x2: decode OP3 {
+                format IntegerOp {
+                        0x00: add({{
+                                INT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                Rd = Rs1.sdw + val2;
+                        }});//ADD
+                        0x01: and({{
+                                UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
+                                Rd = Rs1.udw & val2;
+                        }});//AND
+                        0x02: or({{
+                                UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
+                                Rd = Rs1.udw | val2;
+                        }});//OR
+                        0x03: xor({{
+                                UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
+                                Rd = Rs1.udw ^ val2;
+                        }});//XOR
+                        0x04: sub({{
+                                INT64 val2 = ~((UINT64)(I ? SIMM13.sdw : Rs2.udw))+1;
+                                Rd = Rs1.sdw + val2;
+                        }});//SUB
+                        0x05: andn({{
+                                UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
+                                Rd = Rs1.udw & ~val2;
+                        }});//ANDN
+                        0x06: orn({{
+                                UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
+                                Rd = Rs1.udw | ~val2;
+                        }});//ORN
+                        0x07: xnor({{
+                                UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
+                                Rd = ~(Rs1.udw ^ val2);
+                        }});//XNOR
+                        0x08: addc({{
+                                INT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                INT64 carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
+                                Rd = Rs1.sdw + val2 + carryin;
+                        }});//ADDC
+                        0x09: mulx({{
+                                INT64 val2 = (I ? SIMM13.sdw : Rs2);
+                                Rd = Rs1 * val2;
+                        }});//MULX
+                        0x0A: umul({{
+                                UINT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2.udw);
+                                Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
+                                xc->regs.MiscRegs.yFields.value = resTemp<63:32>;
+                        }});//UMUL
+                        0x0B: smul({{
+                                INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                rd.sdw = resTemp = Rs1.sdw<31:0> * val2<31:0>;
+                                xc->regs.MiscRegs.yFields.value = resTemp<63:32>;
+                        }});//SMUL
+                        0x0C: subc({{
+                                INT64 val2 = ~((INT64)(I ? SIMM13.sdw : Rs2.sdw))+1;
+                                INT64 carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
+                                Rd.sdw = Rs1.sdw + val2 + carryin;
+                        }});//SUBC
+                        0x0D: udivx({{
+                                UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
+                                if(val2 == 0) throw division_by_zero;
+                                Rd.udw = Rs1.udw / val2;
+                        }});//UDIVX
+                        0x0E: udiv({{
+                                UINT32 resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
+                                if(val2 == 0) throw division_by_zero;
+                                resTemp = (UINT64)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.udw<31:0>) / val2;
+                                INT32 overflow = (resTemp<63:32> != 0);
+                                if(overflow) rd.udw = resTemp = 0xFFFFFFFF;
+                                else rd.udw = resTemp;
+                        }});   //UDIV
+                        0x0F: sdiv({{
+                                INT32 resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
+                                if(val2 == 0) throw division_by_zero;
+                                Rd.sdw = resTemp = (INT64)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.sdw<31:0>) / val2;
+                                INT32 overflow = (resTemp<63:31> != 0);
+                                INT32 underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
+                                if(overflow) rd.udw = resTemp = 0x7FFFFFFF;
+                                else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000;
+                                else rd.udw = resTemp;
+                        }});//SDIV
+                }
+                format IntegerOpCc {
+                        0x10: addcc({{
+                                INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
+                                Rd = resTemp = Rs1 + val2;}},
+                                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
+                                {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
+                                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
+                                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
+                        );//ADDcc
+                        0x11: andcc({{
+                                INT64 val2 = (I ? SIMM13.sdw : Rs2);
+                                Rd = Rs1 & val2;}}
+                        ,{{0}},{{0}},{{0}},{{0}});//ANDcc
+                        0x12: orcc({{
+                                INT64 val2 = (I ? SIMM13.sdw : Rs2);
+                                Rd = Rs1 | val2;}}
+                        ,{{0}},{{0}},{{0}},{{0}});//ORcc
+                        0x13: xorcc({{
+                                INT64 val2 = (I ? SIMM13.sdw : Rs2);
+                                Rd = Rs1 ^ val2;}}
+                        ,{{0}},{{0}},{{0}},{{0}});//XORcc
+                        0x14: subcc({{
+                                INT64 resTemp, val2 = (INT64)(I ? SIMM13.sdw : Rs2);
+                                Rd = resTemp = Rs1 - val2;}},
+                                {{((Rs1 & 0xFFFFFFFF + (~val2) & 0xFFFFFFFF + 1) >> 31)}},
+                                {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
+                                {{((Rs1 >> 1) + (~val2) >> 1) + ((Rs1 | ~val2) & 0x1))<63:>}},
+                                {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
+                        );//SUBcc
+                        0x15: andncc({{
+                                INT64 val2 = (I ? SIMM13.sdw : Rs2);
+                                Rd = Rs1 & ~val2;}}
+                        ,{{0}},{{0}},{{0}},{{0}});//ANDNcc
+                        0x16: orncc({{
+                                INT64 val2 = (I ? SIMM13.sdw : Rs2);
+                                Rd = Rs1 | ~val2;}}
+                        ,{{0}},{{0}},{{0}},{{0}});//ORNcc
+                        0x17: xnorcc({{
+                                INT64 val2 = (I ? SIMM13.sdw : Rs2);
+                                Rd = ~(Rs1 ^ val2);}}
+                        ,{{0}},{{0}},{{0}},{{0}});//XNORcc
+                        0x18: addccc({{
+                                INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
+                                INT64 carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
+                                Rd = resTemp = Rs1 + val2 + carryin;}},
+                                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31 + carryin)}},
+                                {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
+                                {{((Rs1 >> 1) + (val2 >> 1) + ((Rs1 & val2) | (carryin & (Rs1 | val2)) & 0x1))<63:>}},
+                                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
+                        );//ADDCcc
+                        0x1A: umulcc({{
+                                UINT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
+                                Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
+                                xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}}
+                        ,{{0}},{{0}},{{0}},{{0}});//UMULcc
+                        0x1B: smulcc({{
+                                INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
+                                Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>;
+                                xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}}
+                        ,{{0}},{{0}},{{0}},{{0}});//SMULcc
+                        0x1C: subccc({{
+                                INT64 resTemp, val2 = (INT64)(I ? SIMM13.sdw : Rs2);
+                                INT64 carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
+                                Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
+                                {{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}},
+                                {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
+                                {{((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}},
+                                {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
+                        );//SUBCcc
+                        0x1D: udivxcc({{
+                                UINT64 val2 = (I ? SIMM13.sdw : Rs2.udw);
+                                if(val2 == 0) throw division_by_zero;
+                                Rd.udw = Rs1.udw / val2;}}
+                        ,{{0}},{{0}},{{0}},{{0}});//UDIVXcc
+                        0x1E: udivcc({{
+                                UINT32 resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
+                                if(val2 == 0) throw division_by_zero;
+                                resTemp = (UINT64)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.udw<31:0>) / val2;
+                                INT32 overflow = (resTemp<63:32> != 0);
+                                if(overflow) rd.udw = resTemp = 0xFFFFFFFF;
+                                else rd.udw = resTemp;}},
+                                {{0}},
+                                {{overflow}},
+                                {{0}},
+                                {{0}}
+                        );//UDIVcc
+                        0x1F: sdivcc({{
+                                INT32 resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
+                                if(val2 == 0) throw division_by_zero;
+                                Rd.sdw = resTemp = (INT64)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.sdw<31:0>) / val2;
+                                INT32 overflow = (resTemp<63:31> != 0);
+                                INT32 underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
+                                if(overflow) rd.udw = resTemp = 0x7FFFFFFF;
+                                else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000;
+                                else rd.udw = resTemp;}},
+                                {{0}},
+                                {{overflow || underflow}},
+                                {{0}},
+                                {{0}}
+                        );//SDIVcc
+                        0x20: taddcc({{
+                                INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
+                                Rd = resTemp = Rs1 + val2;
+                                INT32 overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
+                                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
+                                {{overflow}},
+                                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
+                                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
+                        );//TADDcc
+                        0x21: tsubcc({{
+                                INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
+                                Rd = resTemp = Rs1 + val2;
+                                INT32 overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
+                                {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
+                                {{overflow}},
+                                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
+                                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
+                        );//TSUBcc
+                        0x22: taddcctv({{
+                                INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
+                                Rd = resTemp = Rs1 + val2;
+                                INT32 overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
+                                if(overflow) throw tag_overflow;}},
+                                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
+                                {{overflow}},
+                                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
+                                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
+                        );//TADDccTV
+                        0x23: tsubcctv({{
+                                INT64 resTemp, val2 = (I ? SIMM13.sdw : Rs2);
+                                Rd = resTemp = Rs1 + val2;
+                                INT32 overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
+                                if(overflow) throw tag_overflow;}},
+                                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
+                                {{overflow}},
+                                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
+                                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
+                        );//TSUBccTV
+                        0x24: mulscc({{
+                                INT64 resTemp, multiplicand = (I ? SIMM13.sdw : Rs2);
+                                INT32 multiplier = Rs1<31:0>;
+                                INT32 savedLSB = Rs1<0:>;
+                                multiplier = multipler<31:1> |
+                                        ((xc->regs.MiscRegs.ccrFields.iccFields.n
+                                        ^ xc->regs.MiscRegs.ccrFields.iccFields.v) << 32);
+                                if(!xc->regs.MiscRegs.yFields.value<0:>)
+                                        multiplicand = 0;
+                                Rd = resTemp = multiplicand + multiplier;
+                                xc->regs.MiscRegs.yFields.value = xc->regs.MiscRegs.yFields.value<31:1> | (savedLSB << 31);}},
+                                {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
+                                {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
+                                {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
+                                {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
+                        );//MULScc
+                }
+                format IntegerOp
+                {
+                        0x25: decode X {
+                                0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); //SLL
+                                0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); //SLLX
+                        }
+                        0x26: decode X {
+                                0x0: srl({{Rd = Rs1.udw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRL
+                                0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRLX
+                        }
+                        0x27: decode X {
+                                0x0: sra({{Rd = Rs1.sdw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRA
+                                0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRAX
+                        }
+                        0x28: decode RS1 {
+                                0x0: rdy({{Rd = xc->regs.MiscRegs.yFields.value;}}); //RDY
+                                0x2: rdccr({{Rd = xc->regs.MiscRegs.ccr;}}); //RDCCR
+                                0x3: rdasi({{Rd = xc->regs.MiscRegs.asi;}}); //RDASI
+                                0x4: rdtick({{
+                                        if(xc->regs.MiscRegs.pstateFields.priv == 0 &&
+                                                xc->regs.MiscRegs.tickFields.npt == 1)
+                                                throw privileged_action;
+                                        Rd = xc->regs.MiscRegs.tick;
+                                }});//RDTICK
+                                0x5: rdpc({{Rd = xc->regs.pc;}}); //RDPC
+                                0x6: rdfprs({{Rd = xc->regs.MiscRegs.fprs;}}); //RDFPRS
+                                0xF: decode I {
+                                        0x0: Noop::membar({{//Membar isn't needed yet}}); //MEMBAR
+                                        0x1: Noop::stbar({{//Stbar isn/'t needed yet}}); //STBAR
+                                }
+                        }
+
+                        0x2A: decode RS1 {
+                                0x0: rdprtpc({{checkPriv Rd = xc->regs.MiscRegs.tpc[xc->regs.MiscRegs.tl];}});
+                                0x1: rdprtnpc({{checkPriv Rd = xc->regs.MiscRegs.tnpc[xc->regs.MiscRegs.tl];}});
+                                0x2: rdprtstate({{checkPriv Rd = xc->regs.MiscRegs.tstate[xc->regs.MiscRegs.tl];}});
+                                0x3: rdprtt({{checkPriv Rd = xc->regs.MiscRegs.tt[xc->regs.MiscRegs.tl];}});
+                                0x4: rdprtick({{checkPriv Rd = xc->regs.MiscRegs.tick;}});
+                                0x5: rdprtba({{checkPriv Rd = xc->regs.MiscRegs.tba;}});
+                                0x6: rdprpstate({{checkPriv Rd = xc->regs.MiscRegs.pstate;}});
+                                0x7: rdprtl({{checkPriv Rd = xc->regs.MiscRegs.tl;}});
+                                0x8: rdprpil({{checkPriv Rd = xc->regs.MiscRegs.pil;}});
+                                0x9: rdprcwp({{checkPriv Rd = xc->regs.MiscRegs.cwp;}});
+                                0xA: rdprcansave({{checkPriv Rd = xc->regs.MiscRegs.cansave;}});
+                                0xB: rdprcanrestore({{checkPriv Rd = xc->regs.MiscRegs.canrestore;}});
+                                0xC: rdprcleanwin({{checkPriv Rd = xc->regs.MiscRegs.cleanwin;}});
+                                0xD: rdprotherwin({{checkPriv Rd = xc->regs.MiscRegs.otherwin;}});
+                                0xE: rdprwstate({{checkPriv Rd = xc->regs.MiscRegs.wstate;}});
+                                0xF: rdprfq({{throw illegal_instruction;}}); //The floating point queue isn't implemented right now.
+                        }
+                        0x2B: BasicOperate::flushw({{\\window toilet}}); //FLUSHW
+                        0x2C: movcc({{
+                                ccBank = (CC24 << 2) | (CC14 << 1) | (CC04 << 0);
+                                switch(ccBank)
+                                {
+                                        case 0: case 1: case 2: case 3:
+                                                throw fp_disabled;
+                                        break;
+                                        case 5: case 7:
+                                                throw illegal_instruction;
+                                        break;
+                                        case 4:
+                                                if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND4))
+                                                        Rd = (I ? SIMM11.sdw : RS2);
+                                        break;
+                                        case 6:
+                                                if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, COND4))
+                                                        Rd = (I ? SIMM11.sdw : RS2);
+                                        break;
+                                }
+                        }});//MOVcc
+                        0x2D: sdivx({{
+                                INT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                if(val2 == 0) throw division_by_zero;
+                                Rd.sdw = Rs1.sdw / val2;
+                        }});//SDIVX
+                        0x2E: decode RS1 {
+                                0x0: IntegerOp::popc({{
+                                INT64 count = 0, val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                UINT8 oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}
+                                for(unsigned int x = 0; x < 16; x++)
+                                {
+                                        count += oneBits[val2 & 0xF];
+                                        val2 >> 4;
+                                }
+                                }});//POPC
+                        }
+                        0x2F: movr({{
+                                UINT64 val2 = (I ? SIMM10.sdw : Rs2.sdw);
+                                switch(RCOND)
+                                {
+                                        case 0: case 4:
+                                                throw illegal_instruction;
+                                        break;
+                                        case 1:
+                                                if(Rs1 == 0) Rd = val2;
+                                        break;
+                                        case 2:
+                                                if(Rs1 <= 0) Rd = val2;
+                                        break;
+                                        case 3:
+                                                if(Rs1 = 0) Rd = val2;
+                                        break;
+                                        case 5:
+                                                if(Rs1 != 0) Rd = val2;
+                                        break;
+                                        case 6:
+                                                if(Rs1 > 0) Rd = val2;
+                                        break;
+                                        case 7:
+                                                if(Rs1 >= 0) Rd = val2;
+                                        break;
+                                }
+                        }});//MOVR
+                        0x30: decode RD {
+                                0x0: wry({{
+                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                        xc->regs.MiscRegs.y = Rs1 ^ val2;
+                                }});//WRY
+                                0x2: wrccr({{
+                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                        xc->regs.MiscRegs.ccr = Rs1 ^ val2;
+                                }});//WRCCR
+                                0x3: wrasi({{
+                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                        xc->regs.MiscRegs.asi = Rs1 ^ val2;
+                                }});//WRASI
+                                0x6: wrfprs({{
+                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                        xc->regs.MiscRegs.asi = Rs1 ^ val2;
+                                }});//WRFPRS
+                                0xF: Trap::sir({{software_initiated_reset}}); //SIR
+                        }
+                        0x31: decode FCN {
+                                0x0: BasicOperate::saved({{\\Boogy Boogy}}); //SAVED
+                                0x1: BasicOperate::restored({{\\Boogy Boogy}}); //RESTORED
+                        }
+                        0x32: decode RD {
+                                0x0: wrprtpc({{checkPriv
+                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                        xc->regs.MiscRegs.tpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
+                                }});
+                                0x1: wrprtnpc({{checkPriv
+                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                        xc->regs.MiscRegs.tnpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
+                                }});
+                                0x2: wrprtstate({{checkPriv
+                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                        xc->regs.MiscRegs.tstate[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
+                                }});
+                                0x3: wrprtt({{checkPriv
+                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                        xc->regs.MiscRegs.tt[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
+                                }});
+                                0x4: wrprtick({{checkPriv
+                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                        xc->regs.MiscRegs.tick = Rs1 ^ val2;
+                                }});
+                                0x5: wrprtba({{checkPriv
+                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                        xc->regs.MiscRegs.tba = Rs1 ^ val2;
+                                }});
+                                0x6: wrprpstate({{checkPriv
+                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                        xc->regs.MiscRegs.pstate = Rs1 ^ val2;
+                                }});
+                                0x7: wrprtl({{checkPriv
+                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                        xc->regs.MiscRegs.tl = Rs1 ^ val2;
+                                }});
+                                0x8: wrprpil({{checkPriv
+                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                        xc->regs.MiscRegs.pil = Rs1 ^ val2;
+                                }});
+                                0x9: wrprcwp({{checkPriv
+                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                        xc->regs.MiscRegs.cwp = Rs1 ^ val2;
+                                }});
+                                0xA: wrprcansave({{checkPriv
+                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                        xc->regs.MiscRegs.cansave = Rs1 ^ val2;
+                                }});
+                                0xB: wrprcanrestore({{checkPriv
+                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                        xc->regs.MiscRegs.canrestore = Rs1 ^ val2;
+                                }});
+                                0xC: wrprcleanwin({{checkPriv
+                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                        xc->regs.MiscRegs.cleanwin = Rs1 ^ val2;
+                                }});
+                                0xD: wrprotherwin({{checkPriv
+                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                        xc->regs.MiscRegs.otherwin = Rs1 ^ val2;
+                                }});
+                                0xE: wrprwstate({{checkPriv
+                                        UINT64 val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                        xc->regs.MiscRegs.wstate = Rs1 ^ val2;
+                                }});
+                        }
+
+                        0x34: Trap::fpop1({{Throw fp_disabled;}}); //FPOP1
+                        0x35: Trap::fpop2({{Throw fp_disabled;}}); //FPOP2
+
+
+                        0x38: Branch::jmpl({{//Stuff}}); //JMPL
+                        0x39: Branch::return({{//Other Stuff}}); //RETURN
+                        0x3A: Trap::tcc({{
+                                switch((CC14 << 1) | (CC04 << 0))
+                                {
+                                        case 1: case 3:
+                                                throw illegal_instruction;
+                                        case 0:
+                                                if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, machInst<25:28>))
+                                                        throw trap_instruction;
+                                        break;
+                                        case 2:
+                                                if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, machInst<25:28>))
+                                                        throw trap_instruction;
+                                        break;
+                                }
+                        }}); //Tcc
+                        0x3B: BasicOperate::flush({{//Lala}}); //FLUSH
+                        0x3C: BasicOperate::save({{//leprechauns); //SAVE
+                        0x3D: BasicOperate::restore({{//Eat my short int}}); //RESTORE
+                        0x3E: decode FCN {
+                                0x1: BasicOperate::done({{//Done thing}}); //DONE
+                                0x2: BasicOperate::retry({{//Retry thing}}); //RETRY
+                        }
+                }
+        }
+        0x3: decode OP3 {
+                format Mem {
+                        0x00: lduw({{Rd.uw = Mem.uw;}}); //LDUW
+                        0x01: ldub({{Rd.ub = Mem.ub;}}); //LDUB
+                        0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH
+                        0x03: ldd({{
+                                UINT64 val = Mem.udw;
+                                setIntReg(RD & (~1), val<31:0>);
+                                setIntReg(RD | 1, val<63:32>);
+                        }});//LDD
+                        0x04: stw({{Mem.sw = Rd.sw;}}); //STW
+                        0x05: stb({{Mem.sb = Rd.sb;}}); //STB
+                        0x06: sth({{Mem.shw = Rd.shw;}}); //STH
+                        0x07: std({{
+                                Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
+                        }});//STD
+                        0x08: ldsw({{Rd.sw = Mem.sw;}}); //LDSW
+                        0x09: ldsb({{Rd.sb = Mem.sb;}}); //LDSB
+                        0x0A: ldsh({{Rd.shw = Mem.shw;}}); //LDSH
+                        0x0B: ldx({{Rd.udw = Mem.udw;}}); //LDX
+
+                        0x0D: ldstub({{
+                                Rd.ub = Mem.ub;
+                                Mem.ub = 0xFF;
+                        }}); //LDSTUB
+                        0x0E: stx({{Rd.udw = Mem.udw;}}); //STX
+                        0x0F: swap({{
+                                UINT32 temp = Rd.uw;
+                                Rd.uw = Mem.uw;
+                                Mem.uw = temp;
+                        }}); //SWAP
+                        0x10: lduwa({{Rd.uw = Mem.uw;}}); //LDUWA
+                        0x11: lduba({{Rd.ub = Mem.ub;}}); //LDUBA
+                        0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA
+                        0x13: ldda({{
+                                UINT64 val = Mem.udw;
+                                setIntReg(RD & (~1), val<31:0>);
+                                setIntReg(RD | 1, val<63:32>);
+                        }}); //LDDA
+                        0x14: stwa({{Mem.uw = Rd.uw;}}); //STWA
+                        0x15: stba({{Mem.ub = Rd.ub;}}); //STBA
+                        0x16: stha({{Mem.uhw = Rd.uhw;}}); //STHA
+                        0x17: stda({{
+                                Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
+                        }}); //STDA
+                        0x18: ldswa({{Rd.sw = Mem.sw;}}); //LDSWA
+                        0x19: ldsba({{Rd.sb = Mem.sb;}}); //LDSBA
+                        0x1A: ldsha({{Rd.shw = Mem.shw;}}); //LDSHA
+                        0x1B: ldxa({{Rd.sdw = Mem.sdw;}}); //LDXA
+
+                        0x1D: ldstuba({{
+                                Rd.ub = Mem.ub;
+                                Mem.ub = 0xFF;
+                        }}); //LDSTUBA
+                        0x1E: stxa({{Mem.sdw = Rd.sdw}}); //STXA
+                        0x1F: swapa({{
+                                UINT32 temp = Rd.uw;
+                                Rd.uw = Mem.uw;
+                                Mem.uw = temp;
+                        }}); //SWAPA
+                        0x20: Trap::ldf({{throw fp_disabled;}}); //LDF
+                        0x21: decode X {
+                                0x0: Trap::ldfsr({{throw fp_disabled;}}); //LDFSR
+                                0x1: Trap::ldxfsr({{throw fp_disabled;}}); //LDXFSR
+                        }
+                        0x22: Trap::ldqf({{throw fp_disabled;}}); //LDQF
+                        0x23: Trap::lddf({{throw fp_disabled;}}); //LDDF
+                        0x24: Trap::stf({{throw fp_disabled;}}); //STF
+                        0x25: decode X {
+                                0x0: Trap::stfsr({{throw fp_disabled;}}); //STFSR
+                                0x1: Trap::stxfsr({{throw fp_disabled;}}); //STXFSR
+                        }
+                        0x26: Trap::stqf({{throw fp_disabled;}}); //STQF
+                        0x27: Trap::stdf({{throw fp_disabled;}}); //STDF
+
+
+
+
+
+                        0x2D: Noop::prefetch({{ }}); //PREFETCH
+
+
+                        0x30: Trap::ldfa({{throw fp_disabled;}}); //LDFA
+
+                        0x32: Trap::ldqfa({{throw fp_disabled;}}); //LDQFA
+                        0x33: Trap::lddfa({{throw fp_disabled;}}); //LDDFA
+                        0x34: Trap::stfa({{throw fp_disabled;}}); //STFA
+                        0x35: Trap::stqfa({{throw fp_disabled;}}); //STQFA
+                        0x36: Trap::stdfa({{throw fp_disabled;}}); //STDFA
+
+
+
+
+
+                        0x3C: Cas::casa(
+                                {{UINT64 val = Mem.uw;
+                                if(Rs2.uw == val)
+                                        Mem.uw = Rd.uw;
+                                Rd.uw = val;
+                        }}); //CASA
+                        0x3D: Noop::prefetcha({{ }}); //PREFETCHA
+                        0x3E: Cas::casxa(
+                                {{UINT64 val = Mem.udw;
+                                if(Rs2 == val)
+                                        Mem.udw = Rd;
+                                Rd = val;
+                        }}); //CASXA
+                }
+        }
+}
diff --git a/arch/sparc/isa/formats.isa b/arch/sparc/isa/formats.isa
new file mode 100644
index 000000000..a21e1c110
--- /dev/null
+++ b/arch/sparc/isa/formats.isa
@@ -0,0 +1,19 @@
+//Include the basic format
+//Templates from this format are used later
+##include "m5/arch/sparc/isa_desc/formats/basic.isa"
+
+//Include the integerOp and integerOpCc format
+##include "m5/arch/sparc/isa_desc/formats/integerop.isa"
+
+//Include the mem format
+##include "m5/arch/sparc/isa_desc/formats/mem.isa"
+
+//Include the trap format
+##include "m5/arch/sparc/isa_desc/formats/trap.isa"
+
+//Include the branch format
+##include "m5/arch/sparc/isa_desc/formats/branch.isa"
+
+//Include the noop format
+##include "m5/arch/sparc/isa_desc/formats/noop.isa"
+
diff --git a/arch/sparc/isa/formats/basic.isa b/arch/sparc/isa/formats/basic.isa
new file mode 100644
index 000000000..1994df41c
--- /dev/null
+++ b/arch/sparc/isa/formats/basic.isa
@@ -0,0 +1,65 @@
+
+// Declarations for execute() methods.
+def template BasicExecDeclare {{
+        Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+}};
+
+// Basic instruction class declaration template.
+def template BasicDeclare {{
+        /**
+         * Static instruction class for "%(mnemonic)s".
+         */
+        class %(class_name)s : public %(base_class)s
+        {
+        public:
+                /// Constructor.
+                %(class_name)s(MachInst machInst);
+                %(BasicExecDeclare)s
+    };
+}};
+
+// Basic instruction class constructor template.
+def template BasicConstructor {{
+        inline %(class_name)s::%(class_name)s(MachInst machInst)  : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+        {
+                %(constructor)s;
+        }
+}};
+
+// Basic instruction class execute method template.
+def template BasicExecute {{
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+        {
+                Fault fault = No_Fault;
+
+                %(fp_enable_check)s;
+                %(op_decl)s;
+                %(op_rd)s;
+                %(code)s;
+
+                if(fault == No_Fault)
+                {
+                        %(op_wb)s;
+                }
+                return fault;
+        }
+}};
+
+// Basic decode template.
+def template BasicDecode {{
+        return new %(class_name)s(machInst);
+}};
+
+// Basic decode template, passing mnemonic in as string arg to constructor.
+def template BasicDecodeWithMnemonic {{
+        return new %(class_name)s("%(mnemonic)s", machInst);
+}};
+
+// The most basic instruction format... used only for a few misc. insts
+def format BasicOperate(code, *flags) {{
+        iop = InstObjParams(name, Name, 'SparcStaticInst', CodeBlock(code), flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecode.subst(iop)
+        exec_output = BasicExecute.subst(iop)
+}};
diff --git a/arch/sparc/isa/formats/branch.isa b/arch/sparc/isa/formats/branch.isa
new file mode 100644
index 000000000..c4c0a90af
--- /dev/null
+++ b/arch/sparc/isa/formats/branch.isa
@@ -0,0 +1,66 @@
+////////////////////////////////////////////////////////////////////
+//
+// Branch instructions
+//
+
+output header {{
+        /**
+         * Base class for integer operations.
+         */
+        class Branch : public SparcStaticInst
+        {
+                protected:
+
+                /// Constructor
+                Branch(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
+                {
+                }
+
+                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        };
+}};
+
+output decoder {{
+        std::string Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+                return "Disassembly of integer instruction\n";
+        }
+}};
+
+def template BranchExecute {{
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+        {
+                //Attempt to execute the instruction
+                try
+                {
+                        checkPriv;
+
+                        %(op_decl)s;
+                        %(op_rd)s;
+                        %(code)s;
+                }
+                //If we have an exception for some reason,
+                //deal with it
+                catch(SparcException except)
+                {
+                        //Deal with exception
+                        return No_Fault;
+                }
+
+                //Write the resulting state to the execution context
+                %(op_wb)s;
+
+                return No_Fault;
+        }
+}};
+
+// Primary format for integer operate instructions:
+def format Branch(code, *opt_flags) {{
+        orig_code = code
+        cblk = CodeBlock(code)
+        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        exec_output = BranchExecute.subst(iop)
+}};
diff --git a/arch/sparc/isa/formats/integerop.isa b/arch/sparc/isa/formats/integerop.isa
new file mode 100644
index 000000000..275a346d3
--- /dev/null
+++ b/arch/sparc/isa/formats/integerop.isa
@@ -0,0 +1,110 @@
+////////////////////////////////////////////////////////////////////
+//
+// Integer operate instructions
+//
+
+output header {{
+        /**
+         * Base class for integer operations.
+         */
+        class IntegerOp : public SparcStaticInst
+        {
+                protected:
+
+                /// Constructor
+                IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
+                {
+                }
+
+                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        };
+}};
+
+output decoder {{
+        std::string IntegerOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+                return "Disassembly of integer instruction\n";
+        }
+}};
+
+def template IntegerExecute {{
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+        {
+                //These are set to constants when the execute method
+                //is generated
+                bool useCc = ;
+                bool checkPriv = ;
+
+                //Attempt to execute the instruction
+                try
+                {
+                        checkPriv;
+
+                        %(op_decl)s;
+                        %(op_rd)s;
+                        %(code)s;
+                }
+                //If we have an exception for some reason,
+                //deal with it
+                catch(SparcException except)
+                {
+                        //Deal with exception
+                        return No_Fault;
+                }
+
+                //Write the resulting state to the execution context
+                %(op_wb)s;
+                if(useCc)
+                {
+                        xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63);
+                        xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0);
+                        xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue;
+                        xc->regs.miscRegFile.ccrFields.iccFields.c = icValue;
+                        xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31);
+                        xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0);
+                        xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue;
+                        xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue;
+                }
+                return No_Fault;
+        }
+}};
+
+// Primary format for integer operate instructions:
+def format IntegerOp(code, *opt_flags) {{
+        orig_code = code
+        cblk = CodeBlock(code)
+        checkPriv = (code.find('checkPriv') != -1)
+        code.replace('checkPriv', '')
+        if checkPriv:
+                code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
+        else:
+                code.replace('checkPriv;', '')
+        for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
+                       ('xvValue', '0'), ('xcValue', '0')):
+                code.replace(marker, value)
+        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        exec_output = IntegerExecute.subst(iop)
+}};
+
+// Primary format for integer operate instructions:
+def format IntegerOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
+        orig_code = code
+        cblk = CodeBlock(code)
+        checkPriv = (code.find('checkPriv') != -1)
+        code.replace('checkPriv', '')
+        if checkPriv:
+                code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
+        else:
+                code.replace('checkPriv;', '')
+        for (marker, value) in (('ivValue', ivValue), ('icValue', icValue),
+                       ('xvValue', xvValue), ('xcValue', xcValue)):
+                code.replace(marker, value)
+        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        exec_output = IntegerExecute.subst(iop)
+}};
diff --git a/arch/sparc/isa/formats/mem.isa b/arch/sparc/isa/formats/mem.isa
new file mode 100644
index 000000000..abc00b6f2
--- /dev/null
+++ b/arch/sparc/isa/formats/mem.isa
@@ -0,0 +1,78 @@
+////////////////////////////////////////////////////////////////////
+//
+// Mem instructions
+//
+
+output header {{
+        /**
+         * Base class for integer operations.
+         */
+        class Mem : public SparcStaticInst
+        {
+                protected:
+
+                /// Constructor
+                Mem(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
+                {
+                }
+
+                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        };
+}};
+
+output decoder {{
+        std::string Mem::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+                return "Disassembly of integer instruction\n";
+        }
+}};
+
+def template MemExecute {{
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+        {
+                //Attempt to execute the instruction
+                try
+                {
+
+                        %(op_decl)s;
+                        %(op_rd)s;
+                        ea_code
+                        %(code)s;
+                }
+                //If we have an exception for some reason,
+                //deal with it
+                catch(SparcException except)
+                {
+                        //Deal with exception
+                        return No_Fault;
+                }
+
+                //Write the resulting state to the execution context
+                %(op_wb)s;
+
+                return No_Fault;
+        }
+}};
+
+// Primary format for integer operate instructions:
+def format Mem(code, *opt_flags) {{
+        orig_code = code
+        cblk = CodeBlock(code)
+        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        exec_output = MemExecute.subst(iop)
+        exec_output.replace('ea_code', 'EA = I ? (R1 + SIMM13) : R1 + R2;');
+}};
+
+def format Cas(code, *opt_flags) {{
+        orig_code = code
+        cblk = CodeBlock(code)
+        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        exec_output = MemExecute.subst(iop)
+        exec_output.replace('ea_code', 'EA = R1;');
+}};
diff --git a/arch/sparc/isa/formats/noop.isa b/arch/sparc/isa/formats/noop.isa
new file mode 100644
index 000000000..bc83e3261
--- /dev/null
+++ b/arch/sparc/isa/formats/noop.isa
@@ -0,0 +1,47 @@
+////////////////////////////////////////////////////////////////////
+//
+// Noop instruction
+//
+
+output header {{
+        /**
+         * Base class for integer operations.
+         */
+        class Noop : public SparcStaticInst
+        {
+                protected:
+
+                /// Constructor
+                Noop(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
+                {
+                }
+
+                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        };
+}};
+
+output decoder {{
+        std::string Noop::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+                return "Disassembly of integer instruction\n";
+        }
+}};
+
+def template NoopExecute {{
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+        {
+                //Nothing to see here, move along
+                return No_Fault;
+        }
+}};
+
+// Primary format for integer operate instructions:
+def format Noop(code, *opt_flags) {{
+        orig_code = code
+        cblk = CodeBlock(code)
+        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        exec_output = NoopExecute.subst(iop)
+}};
diff --git a/arch/sparc/isa/formats/trap.isa b/arch/sparc/isa/formats/trap.isa
new file mode 100644
index 000000000..bee77fe69
--- /dev/null
+++ b/arch/sparc/isa/formats/trap.isa
@@ -0,0 +1,53 @@
+////////////////////////////////////////////////////////////////////
+//
+// Trap instructions
+//
+
+output header {{
+        /**
+         * Base class for integer operations.
+         */
+        class Trap : public SparcStaticInst
+        {
+                protected:
+
+                /// Constructor
+                Trap(const char *mnem, MachInst _machInst, OpClass __opClass) : SparcStaticInst(mnem, _machInst, __opClass)
+                {
+                }
+
+                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+        };
+}};
+
+output decoder {{
+        std::string Trap::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+        {
+                return "Disassembly of integer instruction\n";
+        }
+}};
+
+def template TrapExecute {{
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+        {
+                //Call into the trap handler with the appropriate fault
+                return No_Fault;
+        }
+
+                //Write the resulting state to the execution context
+                %(op_wb)s;
+
+                return No_Fault;
+        }
+}};
+
+// Primary format for integer operate instructions:
+def format Trap(code, *opt_flags) {{
+        orig_code = code
+        cblk = CodeBlock(code)
+        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        exec_output = TrapExecute.subst(iop)
+}};
diff --git a/arch/sparc/isa/includes.isa b/arch/sparc/isa/includes.isa
new file mode 100644
index 000000000..ff7cb7d1d
--- /dev/null
+++ b/arch/sparc/isa/includes.isa
@@ -0,0 +1,40 @@
+////////////////////////////////////////////////////////////////////
+//
+// Output include file directives.
+//
+
+output header {{
+#include <sstream>
+#include <iostream>
+#include <iomanip>
+
+#include "cpu/static_inst.hh"
+#include "traps.hh"
+#include "mem/mem_req.hh"  // some constructors use MemReq flags
+}};
+
+output decoder {{
+#include "base/cprintf.hh"
+#include "base/loader/symtab.hh"
+#include "cpu/exec_context.hh"  // for Jump::branchTarget()
+
+#include <math.h>
+#if defined(linux)
+#include <fenv.h>
+#endif
+}};
+
+output exec {{
+#include <math.h>
+#if defined(linux)
+#include <fenv.h>
+#endif
+
+#ifdef FULL_SYSTEM
+//#include "arch/alpha/pseudo_inst.hh"
+#endif
+#include "cpu/base.hh"
+#include "cpu/exetrace.hh"
+#include "sim/sim_exit.hh"
+}};
+
diff --git a/arch/sparc/isa/main.isa b/arch/sparc/isa/main.isa
new file mode 100644
index 000000000..8b6166d34
--- /dev/null
+++ b/arch/sparc/isa/main.isa
@@ -0,0 +1,52 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2003-2005 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+##include "m5/arch/sparc/isa_desc/includes.isa"
+
+////////////////////////////////////////////////////////////////////
+//
+// Namespace statement.  Everything below this line will be in the
+// SparcISAInst namespace.
+//
+
+namespace SparcISA;
+
+//Include the bitfield definitions
+##include "m5/arch/sparc/isa_desc/bitfields.isa"
+
+//Include the operand_types and operand definitions
+##include "m5/arch/sparc/isa_desc/operands.isa"
+
+//Include the base class for sparc instructions, and some support code
+##include "m5/arch/sparc/isa_desc/base.isa"
+
+//Include the definitions for the instruction formats
+##include "m5/arch/sparc/isa_desc/formats.isa"
+
+//Include the decoder definition
+##include "m5/arch/sparc/isa_desc/decoder.isa"
diff --git a/arch/sparc/isa/operands.isa b/arch/sparc/isa/operands.isa
new file mode 100644
index 000000000..77de6c9c4
--- /dev/null
+++ b/arch/sparc/isa/operands.isa
@@ -0,0 +1,33 @@
+def operand_types {{
+    'sb' : ('signed int', 8),
+    'ub' : ('unsigned int', 8),
+    'shw' : ('signed int', 16),
+    'uhw' : ('unsigned int', 16),
+    'sw' : ('signed int', 32),
+    'uw' : ('unsigned int', 32),
+    'sdw' : ('signed int', 64),
+    'udw' : ('unsigned int', 64),
+    'sf' : ('float', 32),
+    'df' : ('float', 64),
+    'qf' : ('float', 128)
+}};
+
+def operands {{
+    # Int regs default to unsigned, but code should not count on this.
+    # For clarity, descriptions that depend on unsigned behavior should
+    # explicitly specify '.uq'.
+    'Rd': IntRegOperandTraits('udw', 'RD', 'IsInteger', 1),
+    'Rs1': IntRegOperandTraits('udw', 'RS1', 'IsInteger', 2),
+    'Rs2': IntRegOperandTraits('udw', 'RS2', 'IsInteger', 3),
+    #'Fa': FloatRegOperandTraits('df', 'FA', 'IsFloating', 1),
+    #'Fb': FloatRegOperandTraits('df', 'FB', 'IsFloating', 2),
+    #'Fc': FloatRegOperandTraits('df', 'FC', 'IsFloating', 3),
+    'Mem': MemOperandTraits('udw', None,
+                            ('IsMemRef', 'IsLoad', 'IsStore'), 4)
+    #'NPC': NPCOperandTraits('uq', None, ( None, None, 'IsControl' ), 4),
+    #'Runiq': ControlRegOperandTraits('uq', 'Uniq', None, 1),
+    #'FPCR':  ControlRegOperandTraits('uq', 'Fpcr', None, 1),
+    # The next two are hacks for non-full-system call-pal emulation
+    #'R0':  IntRegOperandTraits('uq', '0', None, 1),
+    #'R16': IntRegOperandTraits('uq', '16', None, 1)
+}};