SPARC compiles for SE!

arch/sparc/isa/decoder.isa:
    Replaced register number munging with RdLow and RdHigh operands.
arch/sparc/isa/formats/mem.isa:
    Fixed how the address calculation code is dealt with.
arch/sparc/isa/operands.isa:
    Changed the tabbing so that the whole oeprands block was consistent, and added RdLow and RdHigh operands. These registers are used when Rd is meant to refer to a pair of registers, rather than just one.
arch/sparc/isa_traits.hh:
    Moved some functions to the new (to SPARC) utility.hh file. Also, dummy Fpcr_DepTag and Uniq_DepTag DepTags were added to pacify Tru64. These need to be removed, and Tru64 needs to not be compiled in if it isn't appropriate.
arch/sparc/regfile.hh:
    Changed regSpace to have the correct size.
arch/sparc/utility.hh:
    A new file for sparc to match the one for alpha.

--HG--
extra : convert_revision : ff6b529093d15f327ec11f067ad533bacdba9932

3 files changed, 23 insertions, 16 deletions

diff --git a/arch/sparc/isa/decoder.isa b/arch/sparc/isa/decoder.isa
index ca8d22419..6c1356932 100644
--- a/arch/sparc/isa/decoder.isa
+++ b/arch/sparc/isa/decoder.isa
@@ -444,14 +444,14 @@ decode OP default Unknown::unknown()
                     0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH
                     0x03: ldd({{
                         uint64_t val = Mem.udw;
-                        setIntReg(RD & (~1), val<31:0>);
-                        setIntReg(RD | 1, val<63:32>);
+                        RdLow = val<31:0>;
+                        RdHigh = val<63:32>;
                     }});//LDD
                     0x04: stw({{Mem.sw = Rd.sw;}}); //STW
                     0x05: stb({{Mem.sb = Rd.sb;}}); //STB
                     0x06: sth({{Mem.shw = Rd.shw;}}); //STH
                     0x07: std({{
-                            Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
+                            Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;
                     }});//STD
                     0x08: ldsw({{Rd.sw = Mem.sw;}}); //LDSW
                     0x09: ldsb({{Rd.sb = Mem.sb;}}); //LDSB
@@ -473,14 +473,14 @@ decode OP default Unknown::unknown()
                     0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA
                     0x13: ldda({{
                             uint64_t val = Mem.udw;
-                            setIntReg(RD & (~1), val<31:0>);
-                            setIntReg(RD | 1, val<63:32>);
+                            RdLow = val<31:0>;
+                            RdHigh = val<63:32>;
                     }}); //LDDA
                     0x14: stwa({{Mem.uw = Rd.uw;}}); //STWA
                     0x15: stba({{Mem.ub = Rd.ub;}}); //STBA
                     0x16: stha({{Mem.uhw = Rd.uhw;}}); //STHA
                     0x17: stda({{
-                            Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
+                            Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;
                     }}); //STDA
                     0x18: ldswa({{Rd.sw = Mem.sw;}}); //LDSWA
                     0x19: ldsba({{Rd.sb = Mem.sb;}}); //LDSBA
diff --git a/arch/sparc/isa/formats/mem.isa b/arch/sparc/isa/formats/mem.isa
index cf6e7d95b..f1162e24b 100644
--- a/arch/sparc/isa/formats/mem.isa
+++ b/arch/sparc/isa/formats/mem.isa
@@ -52,10 +52,15 @@ def template MemExecute {{
 
 // Primary format for integer operate instructions:
 def format Mem(code, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
-        iop.ea_code = CodeBlock('EA = I ? (R1 + SIMM13) : R1 + R2;').code
+        addrCalc = 'EA = I ? (Rs1 + SIMM13) : Rs1 + Rs2;'
+        composite = code + '\n' + addrCalc
+        origCodeBlk = CodeBlock(code)
+        compositeBlk = CodeBlock(composite)
+        addrCalcBlk = CodeBlock(addrCalc)
+        iop = InstObjParams(name, Name, 'SparcStaticInst', compositeBlk, opt_flags)
+        iop.code = origCodeBlk.code
+        iop.orig_code = origCodeBlk.orig_code
+        iop.ea_code = addrCalcBlk.code
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
         decode_block = BasicDecode.subst(iop)
diff --git a/arch/sparc/isa/operands.isa b/arch/sparc/isa/operands.isa
index abfdf7bcd..0d521fae0 100644
--- a/arch/sparc/isa/operands.isa
+++ b/arch/sparc/isa/operands.isa
@@ -16,18 +16,20 @@ def operands {{
     # Int regs default to unsigned, but code should not count on this.
     # For clarity, descriptions that depend on unsigned behavior should
     # explicitly specify '.uq'.
-    'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
-    'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 2),
-    'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 3),
+    'Rd': 		('IntReg', 'udw', 'RD', 'IsInteger', 1),
+    'RdLow': 		('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 2),
+    'RdHigh':		('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
+    'Rs1': 		('IntReg', 'udw', 'RS1', 'IsInteger', 4),
+    'Rs2': 		('IntReg', 'udw', 'RS2', 'IsInteger', 5),
     #'Fa': ('FloatReg', 'df', 'FA', 'IsFloating', 1),
     #'Fb': ('FloatReg', 'df', 'FB', 'IsFloating', 2),
     #'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
-    'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
+    'Mem': 		('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
     #'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
     #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
     #'FPCR':  ('ControlReg', 'uq', 'Fpcr', None, 1),
-    'R0':  ('IntReg', 'udw', '0', None, 1),
-    'R16': ('IntReg', 'udw', '16', None, 1),
+    'R0':  		('IntReg', 'udw', '0', None, 1),
+    'R16': 		('IntReg', 'udw', '16', None, 1),
     # Control registers
     'Pstate':		('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1),
     'PstateAg':		('ControlReg', 'udw', 'MISCREG_PSTATE_AG', None, 2),