diff options
| author | Korey Sewell <ksewell@umich.edu> | 2006-03-15 23:38:55 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2006-03-15 23:38:55 -0500 |
| commit | 77a2f97c3590d7d51ffc5b447546c7c70894bdbd (patch) | |
| tree | 3463e457b10da0cea34cf20e914b2b51dc329d28 /arch/sparc/isa | |
| parent | e2b558112b408847a1423e5dd12db59e81260c84 (diff) | |
| parent | 7359e2df01fde9ea34a0ba661750a455e26bcacd (diff) | |
| download | gem5-77a2f97c3590d7d51ffc5b447546c7c70894bdbd.tar.xz | |
Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-mips
--HG--
extra : convert_revision : 9bdde9b5bd3049744451eda1134f080b7c4b1b59
Diffstat (limited to 'arch/sparc/isa')
| -rw-r--r-- | arch/sparc/isa/bitfields.isa | 2 | ||||
| -rw-r--r-- | arch/sparc/isa/decoder.isa | 18 |
2 files changed, 17 insertions, 3 deletions
diff --git a/arch/sparc/isa/bitfields.isa b/arch/sparc/isa/bitfields.isa index b0ac57575..237f0fa64 100644 --- a/arch/sparc/isa/bitfields.isa +++ b/arch/sparc/isa/bitfields.isa @@ -46,5 +46,5 @@ def bitfield SHCNT64 <5:0>; def bitfield SIMM10 <9:0>; def bitfield SIMM11 <10:0>; def bitfield SIMM13 <12:0>; -def bitfield SW_TRAP <6:0>; +def bitfield SW_TRAP <7:0>; def bitfield X <12>; diff --git a/arch/sparc/isa/decoder.isa b/arch/sparc/isa/decoder.isa index eaf3aab3b..716653d84 100644 --- a/arch/sparc/isa/decoder.isa +++ b/arch/sparc/isa/decoder.isa @@ -532,12 +532,26 @@ decode OP default Trap::unknown({{IllegalInstruction}}) { case 1: case 3: throw illegal_instruction; case 0: +#if FULL_SYSTEM + throw trap_instruction; +#else if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, machInst<25:28>)) - throw trap_instruction; + // At least glibc only uses trap 0, + // solaris/sunos may use others + assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0); + xc->syscall(); +#endif break; case 2: +#if FULL_SYSTEM + throw trap_instruction; +#else if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, machInst<25:28>)) - throw trap_instruction; + // At least glibc only uses trap 0, + // solaris/sunos may use others + assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0); + xc->syscall(); +#endif break; } }}); //Tcc |