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authorKorey Sewell <ksewell@umich.edu>2006-02-20 14:30:23 -0500
committerKorey Sewell <ksewell@umich.edu>2006-02-20 14:30:23 -0500
commit19534176e06578cb167d5f10d9146f6b1c361cb5 (patch)
treec9bbff469d8d5a05b933aa98c2ed038a1e4e848c /arch/sparc/isa_traits.hh
parent38ce95db3b7cf471dcd3c12b784877c4dc238d6f (diff)
downloadgem5-19534176e06578cb167d5f10d9146f6b1c361cb5.tar.xz
load/store instruction format ... now generates load/store code
and breaks it into a separate EA and MemAccess templated from how the Alpha ARch. was coded to do the same thing. arch/mips/isa/bitfields.isa: comment change arch/mips/isa/decoder.isa: re-structuring of load/store instruction definitions arch/mips/isa/formats/mem.isa: Define LoadMemory & Store Memory formats Use style of formatting & base class similar to what was used for ALPHA arch/mips/isa/formats/util.isa: Insert LoadStoreBase function here from alpha/arch/isa/mem.isa arch/mips/isa/operands.isa: change shw->sh and uhw->uh --HG-- extra : convert_revision : 5d85f15f4a600dd4c473a3b4a170ba39cf07fc8a
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