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authorGabe Black <gblack@eecs.umich.edu>2006-03-07 14:08:01 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-03-07 14:08:01 -0500
commit8106a804508a42455650082a83f4cdb366ca5148 (patch)
treebfe97803535239ff9665fc1e6c278893df832ac7 /arch/sparc
parentcd62fed1a7c535befaa00c8775de78f9f29b1274 (diff)
downloadgem5-8106a804508a42455650082a83f4cdb366ca5148.tar.xz
Pushed ev5.hh out of the non-alpha code.
arch/SConscript: ev5 should now be contained within alpha specific code. arch/alpha/ev5.cc: arch/alpha/isa_traits.hh: Added getInstAsid and getDataAsid functions. These should be removed when the SimpleScalar cpu model is removed. arch/sparc/isa_traits.hh: Added getInstAsid and getDataAsid functions. These should be removed when the SimpleScalar cpu model is removed. Also made some small fixes. cpu/o3/alpha_cpu.hh: Added typedefs which are required now that there isn't a using namespace EV5. cpu/o3/alpha_cpu_impl.hh: Some small changes so that ev5.hh isn't needed directly. cpu/o3/cpu.hh: Removed including ev5.hh, and pushed retrieving the Asid into the MiscRegFile. cpu/o3/regfile.hh: Removed the include of ev5.hh, using namespace EV5, and the now redundant ipr array. --HG-- extra : convert_revision : 5ef8f69435a3a888a3f06d0095d89326dafb33fd
Diffstat (limited to 'arch/sparc')
-rw-r--r--arch/sparc/isa_traits.hh14
1 files changed, 12 insertions, 2 deletions
diff --git a/arch/sparc/isa_traits.hh b/arch/sparc/isa_traits.hh
index 0fdac1662..73daae8a9 100644
--- a/arch/sparc/isa_traits.hh
+++ b/arch/sparc/isa_traits.hh
@@ -57,7 +57,7 @@ class StaticInstPtr;
namespace SparcISA
{
typedef uint32_t MachInst;
- typedef uint64_t Addr;
+ typedef uint64_t ExtMachInst;
typedef uint8_t RegIndex;
enum
@@ -179,7 +179,7 @@ namespace SparcISA
// The control registers, broken out into fields
class MiscRegFile
{
- public:
+ private:
union
{
uint16_t pstate; // Process State Register
@@ -365,6 +365,16 @@ namespace SparcISA
} fprsFields;
};
+ public:
+ MiscReg readReg(int misc_reg);
+
+ MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc);
+
+ Fault setReg(int misc_reg, const MiscReg &val);
+
+ Fault setRegWithEffect(int misc_reg, const MiscReg &val,
+ ExecContext *xc);
+
void serialize(std::ostream & os);
void unserialize(Checkpoint * cp, std::string & section);