Merge m5.eecs.umich.edu:/bk/newmem

into  ewok.(none):/home/gblack/m5/newmem

arch/sparc/isa/decoder.isa:
    SCCS merged

--HG--
extra : convert_revision : 460843b49bc96b3fbc5897828c23f9cf9b010ae0

15 files changed, 996 insertions, 734 deletions

diff --git a/arch/sparc/faults.cc b/arch/sparc/faults.cc
index b48fc600b..9831a7679 100644
--- a/arch/sparc/faults.cc
+++ b/arch/sparc/faults.cc
@@ -89,10 +89,10 @@ TrapType      IllegalInstruction::_trapType = 0x010;
 FaultPriority IllegalInstruction::_priority = 7;
 FaultStat     IllegalInstruction::_count;
 
-FaultName     PrivelegedOpcode::_name = "priv_opcode";
-TrapType      PrivelegedOpcode::_trapType = 0x011;
-FaultPriority PrivelegedOpcode::_priority = 6;
-FaultStat     PrivelegedOpcode::_count;
+FaultName     PrivilegedOpcode::_name = "priv_opcode";
+TrapType      PrivilegedOpcode::_trapType = 0x011;
+FaultPriority PrivilegedOpcode::_priority = 6;
+FaultStat     PrivilegedOpcode::_count;
 
 FaultName     UnimplementedLDD::_name = "unimp_ldd";
 TrapType      UnimplementedLDD::_trapType = 0x012;
@@ -159,10 +159,10 @@ TrapType      STDFMemAddressNotAligned::_trapType = 0x036;
 FaultPriority STDFMemAddressNotAligned::_priority = 10;
 FaultStat     STDFMemAddressNotAligned::_count;
 
-FaultName     PrivelegedAction::_name = "priv_action";
-TrapType      PrivelegedAction::_trapType = 0x037;
-FaultPriority PrivelegedAction::_priority = 11;
-FaultStat     PrivelegedAction::_count;
+FaultName     PrivilegedAction::_name = "priv_action";
+TrapType      PrivilegedAction::_trapType = 0x037;
+FaultPriority PrivilegedAction::_priority = 11;
+FaultStat     PrivilegedAction::_count;
 
 FaultName     LDQFMemAddressNotAligned::_name = "unalign_ldqf";
 TrapType      LDQFMemAddressNotAligned::_trapType = 0x038;
diff --git a/arch/sparc/faults.hh b/arch/sparc/faults.hh
index 318b1ad5a..985407c26 100644
--- a/arch/sparc/faults.hh
+++ b/arch/sparc/faults.hh
@@ -216,7 +216,7 @@ class IllegalInstruction : public SparcFault
     FaultStat & countStat() {return _count;}
 };
 
-class PrivelegedOpcode : public SparcFault
+class PrivilegedOpcode : public SparcFault
 {
   private:
     static FaultName _name;
@@ -412,7 +412,7 @@ class STDFMemAddressNotAligned : public SparcFault
     FaultStat & countStat() {return _count;}
 };
 
-class PrivelegedAction : public SparcFault
+class PrivilegedAction : public SparcFault
 {
   private:
     static FaultName _name;
diff --git a/arch/sparc/isa/base.isa b/arch/sparc/isa/base.isa
index 916a9c5a5..f8c6ae12c 100644
--- a/arch/sparc/isa/base.isa
+++ b/arch/sparc/isa/base.isa
@@ -48,6 +48,8 @@ output header {{
 
             std::string generateDisassembly(Addr pc,
                 const SymbolTable *symtab) const;
+
+            void printReg(std::ostream &os, int reg) const;
         };
 
         bool passesCondition(condCodes codes, condTest condition);
@@ -55,6 +57,17 @@ output header {{
 
 output decoder {{
 
+        void
+        SparcStaticInst::printReg(std::ostream &os, int reg) const
+        {
+            if (reg < FP_Base_DepTag) {
+                ccprintf(os, "r%d", reg);
+            }
+            else {
+                ccprintf(os, "f%d", reg - FP_Base_DepTag);
+            }
+        }
+
         std::string SparcStaticInst::generateDisassembly(Addr pc,
             const SymbolTable *symtab) const
         {
@@ -124,6 +137,8 @@ output decoder {{
               case OverflowSet:
                 return codes.v;
             }
+            panic("Tried testing condition nonexistant "
+                    "condition code %d", condition);
         }
 }};
 
diff --git a/arch/sparc/isa/decoder.isa b/arch/sparc/isa/decoder.isa
index 716653d84..14280ef12 100644
--- a/arch/sparc/isa/decoder.isa
+++ b/arch/sparc/isa/decoder.isa
@@ -3,674 +3,636 @@
 // The actual decoder specification
 //
 
-decode OP default Trap::unknown({{IllegalInstruction}}) {
-
-        0x0: decode OP2 {
-            //0x0: Trap::illtrap({{IllegalInstruction}});  //ILLTRAP
-            0x1: Branch::bpcc({{
-                switch((CC12 << 1) | CC02)
-                {
-                  case 1:
-                  case 3:
-                    fault = new IllegalInstruction;
-                  case 0:
-                    if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND2))
-                        ;//branchHere
-                    break;
-                  case 2:
-                    if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, COND2))
-                        ;//branchHere
-                    break;
-                }
-            }});//BPcc
-            0x2: Branch::bicc({{
-                if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND2))
+decode OP default Unknown::unknown()
+{
+    0x0: decode OP2
+    {
+        //Throw an illegal instruction acception
+        0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
+        0x1: Branch::bpcc({{
+            switch((CC12 << 1) | CC02)
+            {
+              case 1:
+              case 3:
+                fault = new IllegalInstruction;
+              case 0:
+                if(passesCondition(CcrIcc, COND2))
                     ;//branchHere
-            }});//Bicc
-            0x3: Branch::bpr({{
-                switch(RCOND)
-                {
-                  case 0:
-                  case 4:
-                    fault = new IllegalInstruction;
-                  case 1:
-                    if(Rs1 == 0)
-                        ;//branchHere
-                    break;
-                  case 2:
-                    if(Rs1 <= 0)
-                        ;//branchHere
-                    break;
-                  case 3:
-                    if(Rs1 < 0)
-                        ;//branchHere
-                    break;
-                  case 5:
-                    if(Rs1 != 0)
-                        ;//branchHere
-                    break;
-                  case 6:
-                    if(Rs1 > 0)
-                        ;//branchHere
-                    break;
-                  case 7:
-                    if(Rs1 >= 0)
-                        ;//branchHere
-                    break;
-                }
-                }});    //BPr
-                //SETHI (or NOP if rd == 0 and imm == 0)
-                0x4: IntegerOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}});
-                0x5: Trap::fbpfcc({{throw fp_disabled;}}); //FBPfcc
-                0x6: Trap::fbfcc({{throw fp_disabled;}});  //FBfcc
+                break;
+              case 2:
+                if(passesCondition(CcrXcc, COND2))
+                    ;//branchHere
+                break;
+            }
+        }});//BPcc
+        0x2: Branch::bicc({{
+            if(passesCondition(CcrIcc, COND2))
+                ;//branchHere
+        }});//Bicc
+        0x3: Branch::bpr({{
+            switch(RCOND2)
+            {
+              case 0:
+              case 4:
+                fault = new IllegalInstruction;
+              case 1:
+                if(Rs1 == 0)
+                    ;//branchHere
+                break;
+              case 2:
+                if(Rs1 <= 0)
+                    ;//branchHere
+                break;
+              case 3:
+                if(Rs1 < 0)
+                    ;//branchHere
+                break;
+              case 5:
+                if(Rs1 != 0)
+                    ;//branchHere
+                break;
+              case 6:
+                if(Rs1 > 0)
+                    ;//branchHere
+                break;
+              case 7:
+                if(Rs1 >= 0)
+                    ;//branchHere
+                break;
+            }
+            }});    //BPr
+            //SETHI (or NOP if rd == 0 and imm == 0)
+            0x4: IntegerOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}});
+            0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
+            0x6: Trap::fbfcc({{fault = new FpDisabled;}});
+    }
+    0x1: Branch::call({{
+            //branch here
+            Rd = xc->pc;
+    }});
+    0x2: decode OP3 {
+        format IntegerOp {
+            0x00: add({{
+                int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                Rd = Rs1.sdw + val2;
+            }});//ADD
+            0x01: and({{
+                uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
+                Rd = Rs1.udw & val2;
+            }});//AND
+            0x02: or({{
+                uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
+                Rd = Rs1.udw | val2;
+            }});//OR
+            0x03: xor({{
+                uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
+                Rd = Rs1.udw ^ val2;
+            }});//XOR
+            0x04: sub({{
+                int64_t val2 = ~((uint64_t)(I ? SIMM13.sdw : Rs2.udw))+1;
+                Rd = Rs1.sdw + val2;
+            }});//SUB
+            0x05: andn({{
+                uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
+                Rd = Rs1.udw & ~val2;
+            }});//ANDN
+            0x06: orn({{
+                uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
+                Rd = Rs1.udw | ~val2;
+            }});//ORN
+            0x07: xnor({{
+                uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
+                Rd = ~(Rs1.udw ^ val2);
+            }});//XNOR
+            0x08: addc({{
+                int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                int64_t carryin = CcrIccC;
+                Rd = Rs1.sdw + val2 + carryin;
+            }});//ADDC
+            0x09: mulx({{
+                int64_t val2 = (I ? SIMM13.sdw : Rs2);
+                Rd = Rs1 * val2;
+            }});//MULX
+            0x0A: umul({{
+                uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.udw);
+                Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
+                YValue = resTemp<63:32>;
+            }});//UMUL
+            0x0B: smul({{
+                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                rd.sdw = resTemp = Rs1.sdw<31:0> * val2<31:0>;
+                YValue = resTemp<63:32>;
+            }});//SMUL
+            0x0C: subc({{
+                int64_t val2 = ~((int64_t)(I ? SIMM13.sdw : Rs2.sdw))+1;
+                int64_t carryin = CcrIccC;
+                Rd.sdw = Rs1.sdw + val2 + carryin;
+            }});//SUBC
+            0x0D: udivx({{
+                uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
+                if(val2 == 0) fault = new DivisionByZero;
+                else Rd.udw = Rs1.udw / val2;
+            }});//UDIVX
+            0x0E: udiv({{
+                uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
+                if(val2 == 0)
+                    fault = new DivisionByZero;
+                resTemp = (uint64_t)((YValue << 32)
+                    | Rs1.udw<31:0>) / val2;
+                int32_t overflow = (resTemp<63:32> != 0);
+                if(overflow)
+                    rd.udw = resTemp = 0xFFFFFFFF;
+                else
+                    rd.udw = resTemp;
+            }});   //UDIV
+            0x0F: sdiv({{
+                int32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
+                if(val2 == 0)
+                    fault = new DivisionByZero;
+
+                Rd.sdw = (int64_t)((YValue << 32) |
+                    Rs1.sdw<31:0>) / val2;
+                resTemp = Rd.sdw;
+                int32_t overflow = (resTemp<63:31> != 0);
+                int32_t underflow =
+                    (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
+                if(overflow)
+                    rd.udw = resTemp = 0x7FFFFFFF;
+                else if(underflow)
+                    rd.udw = resTemp = 0xFFFFFFFF80000000;
+                else
+                    rd.udw = resTemp;
+            }});//SDIV
         }
-        0x1: Branch::call({{
-                //branch here
-                Rd = xc->pc;
-        }});
-        0x2: decode OP3 {
-            format IntegerOp {
-                0x00: add({{
-                    int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                    Rd = Rs1.sdw + val2;
-                }});//ADD
-                0x01: and({{
-                    uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
-                    Rd = Rs1.udw & val2;
-                }});//AND
-                0x02: or({{
-                    uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
-                    Rd = Rs1.udw | val2;
-                }});//OR
-                0x03: xor({{
-                    uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
-                    Rd = Rs1.udw ^ val2;
-                }});//XOR
-                0x04: sub({{
-                    int64_t val2 = ~((uint64_t)(I ? SIMM13.sdw : Rs2.udw))+1;
-                    Rd = Rs1.sdw + val2;
-                }});//SUB
-                0x05: andn({{
-                    uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
-                    Rd = Rs1.udw & ~val2;
-                }});//ANDN
-                0x06: orn({{
-                    uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
-                    Rd = Rs1.udw | ~val2;
-                }});//ORN
-                0x07: xnor({{
-                    uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
-                    Rd = ~(Rs1.udw ^ val2);
-                }});//XNOR
-                0x08: addc({{
-                    int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                    int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
-                    Rd = Rs1.sdw + val2 + carryin;
-                }});//ADDC
-                0x09: mulx({{
-                    int64_t val2 = (I ? SIMM13.sdw : Rs2);
-                    Rd = Rs1 * val2;
-                }});//MULX
-                0x0A: umul({{
-                    uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.udw);
-                    Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
-                    xc->regs.MiscRegs.yFields.value = resTemp<63:32>;
-                }});//UMUL
-                0x0B: smul({{
-                    int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                    rd.sdw = resTemp = Rs1.sdw<31:0> * val2<31:0>;
-                    xc->regs.MiscRegs.yFields.value = resTemp<63:32>;
-                }});//SMUL
-                0x0C: subc({{
-                    int64_t val2 = ~((int64_t)(I ? SIMM13.sdw : Rs2.sdw))+1;
-                    int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
-                    Rd.sdw = Rs1.sdw + val2 + carryin;
-                }});//SUBC
-                0x0D: udivx({{
-                    uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
-                    if(val2 == 0) throw division_by_zero;
-                    Rd.udw = Rs1.udw / val2;
-                }});//UDIVX
-                0x0E: udiv({{
-                    uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
-                    if(val2 == 0)
-                        fault = new DivisionByZero;
-                    resTemp = (uint64_t)((xc->regs.MiscRegs.yFields.value << 32)
-                        | Rs1.udw<31:0>) / val2;
+        format IntegerOpCc {
+            0x10: addcc({{
+                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
+                Rd = resTemp = Rs1 + val2;}},
+                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
+                {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
+                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
+                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
+                );//ADDcc
+            0x11: andcc({{
+                int64_t val2 = (I ? SIMM13.sdw : Rs2);
+                Rd = Rs1 & val2;}},
+                {{0}},{{0}},{{0}},{{0}});//ANDcc
+            0x12: orcc({{
+                int64_t val2 = (I ? SIMM13.sdw : Rs2);
+                Rd = Rs1 | val2;}},
+                {{0}},{{0}},{{0}},{{0}});//ORcc
+            0x13: xorcc({{
+                int64_t val2 = (I ? SIMM13.sdw : Rs2);
+                Rd = Rs1 ^ val2;}},
+                {{0}},{{0}},{{0}},{{0}});//XORcc
+            0x14: subcc({{
+                int64_t resTemp, val2 = (int64_t)(I ? SIMM13.sdw : Rs2);
+                Rd = resTemp = Rs1 - val2;}},
+                {{((Rs1 & 0xFFFFFFFF + (~val2) & 0xFFFFFFFF + 1) >> 31)}},
+                {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
+                {{((Rs1 >> 1) + (~val2) >> 1) +
+                    ((Rs1 | ~val2) & 0x1))<63:>}},
+                {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
+            );//SUBcc
+            0x15: andncc({{
+                int64_t val2 = (I ? SIMM13.sdw : Rs2);
+                Rd = Rs1 & ~val2;}},
+                {{0}},{{0}},{{0}},{{0}});//ANDNcc
+            0x16: orncc({{
+                int64_t val2 = (I ? SIMM13.sdw : Rs2);
+                Rd = Rs1 | ~val2;}},
+                {{0}},{{0}},{{0}},{{0}});//ORNcc
+            0x17: xnorcc({{
+                int64_t val2 = (I ? SIMM13.sdw : Rs2);
+                Rd = ~(Rs1 ^ val2);}},
+                {{0}},{{0}},{{0}},{{0}});//XNORcc
+            0x18: addccc({{
+                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
+                int64_t carryin = CcrIccC;
+                Rd = resTemp = Rs1 + val2 + carryin;}},
+                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31
+                    + carryin)}},
+                {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
+                {{((Rs1 >> 1) + (val2 >> 1) +
+                    ((Rs1 & val2) | (carryin & (Rs1 | val2)) & 0x1))<63:>}},
+                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
+            );//ADDCcc
+            0x1A: umulcc({{
+                uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
+                Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
+                YValue = resTemp<63:32>;}},
+                {{0}},{{0}},{{0}},{{0}});//UMULcc
+            0x1B: smulcc({{
+                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
+                Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>;
+                YValue = resTemp<63:32>;}}
+                ,{{0}},{{0}},{{0}},{{0}});//SMULcc
+            0x1C: subccc({{
+                int64_t resTemp, val2 = (int64_t)(I ? SIMM13.sdw : Rs2);
+                int64_t carryin = CcrIccC;
+                Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
+                {{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}},
+                {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
+                {{((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}},
+                {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
+            );//SUBCcc
+            0x1D: udivxcc({{
+                uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
+                if(val2 == 0) fault = new DivisionByZero;
+                else Rd.udw = Rs1.udw / val2;}}
+                ,{{0}},{{0}},{{0}},{{0}});//UDIVXcc
+            0x1E: udivcc({{
+                uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
+                if(val2 == 0) fault = new DivisionByZero;
+                else
+                {
+                    resTemp = (uint64_t)((YValue << 32) | Rs1.udw<31:0>) / val2;
                     int32_t overflow = (resTemp<63:32> != 0);
-                    if(overflow)
-                        rd.udw = resTemp = 0xFFFFFFFF;
-                    else
-                        rd.udw = resTemp;
-                }});   //UDIV
-                0x0F: sdiv({{
-                    int32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
-                    if(val2 == 0)
-                        fault = new DivisionByZero;
-
-                    Rd.sdw = (int64_t)((xc->regs.MiscRegs.yFields.value << 32) |
-                        Rs1.sdw<31:0>) / val2;
-                    resTemp = Rd.sdw;
+                    if(overflow) rd.udw = resTemp = 0xFFFFFFFF;
+                    else rd.udw = resTemp;
+                } }},
+                {{0}},
+                {{overflow}},
+                {{0}},
+                {{0}}
+            );//UDIVcc
+            0x1F: sdivcc({{
+                int32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
+                if(val2 == 0) fault = new DivisionByZero;
+                else
+                {
+                    Rd.sdw = resTemp = (int64_t)((YValue << 32) | Rs1.sdw<31:0>) / val2;
                     int32_t overflow = (resTemp<63:31> != 0);
-                    int32_t underflow =
-                        (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
-                    if(overflow)
-                        rd.udw = resTemp = 0x7FFFFFFF;
-                    else if(underflow)
-                        rd.udw = resTemp = 0xFFFFFFFF80000000;
-                    else
-                        rd.udw = resTemp;
-                }});//SDIV
+                    int32_t underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
+                    if(overflow) rd.udw = resTemp = 0x7FFFFFFF;
+                    else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000;
+                    else rd.udw = resTemp;
+                } }},
+                {{0}},
+                {{overflow || underflow}},
+                {{0}},
+                {{0}}
+            );//SDIVcc
+            0x20: taddcc({{
+                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
+                Rd = resTemp = Rs1 + val2;
+                int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
+                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
+                {{overflow}},
+                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
+                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
+            );//TADDcc
+            0x21: tsubcc({{
+                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
+                Rd = resTemp = Rs1 + val2;
+                int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
+                {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
+                {{overflow}},
+                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
+                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
+            );//TSUBcc
+            0x22: taddcctv({{
+                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
+                Rd = resTemp = Rs1 + val2;
+                int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
+                if(overflow) fault = new TagOverflow;}},
+                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
+                {{overflow}},
+                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
+                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
+            );//TADDccTV
+            0x23: tsubcctv({{
+                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
+                Rd = resTemp = Rs1 + val2;
+                int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
+                if(overflow) fault = new TagOverflow;}},
+                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
+                {{overflow}},
+                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
+                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
+            );//TSUBccTV
+            0x24: mulscc({{
+                int64_t resTemp, multiplicand = (I ? SIMM13.sdw : Rs2);
+                int32_t multiplier = Rs1<31:0>;
+                int32_t savedLSB = Rs1<0:>;
+                multiplier = multipler<31:1> |
+                    ((CcrIccN
+                    ^ CcrIccV) << 32);
+                if(!YValue<0:>)
+                    multiplicand = 0;
+                Rd = resTemp = multiplicand + multiplier;
+                YValue = YValue<31:1> | (savedLSB << 31);}},
+                {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
+                {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
+                {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
+                {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
+            );//MULScc
             }
-            format IntegerOpCc {
-                0x10: addcc({{
-                    int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
-                    Rd = resTemp = Rs1 + val2;}},
-                    {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
-                    {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
-                    {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
-                    {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
-                    );//ADDcc
-                0x11: andcc({{
-                    int64_t val2 = (I ? SIMM13.sdw : Rs2);
-                    Rd = Rs1 & val2;}},
-                    {{0}},{{0}},{{0}},{{0}});//ANDcc
-                0x12: orcc({{
-                    int64_t val2 = (I ? SIMM13.sdw : Rs2);
-                    Rd = Rs1 | val2;}},
-                    {{0}},{{0}},{{0}},{{0}});//ORcc
-                0x13: xorcc({{
-                    int64_t val2 = (I ? SIMM13.sdw : Rs2);
-                    Rd = Rs1 ^ val2;}},
-                    {{0}},{{0}},{{0}},{{0}});//XORcc
-                0x14: subcc({{
-                    int64_t resTemp, val2 = (int64_t)(I ? SIMM13.sdw : Rs2);
-                    Rd = resTemp = Rs1 - val2;}},
-                    {{((Rs1 & 0xFFFFFFFF + (~val2) & 0xFFFFFFFF + 1) >> 31)}},
-                    {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
-                    {{((Rs1 >> 1) + (~val2) >> 1) +
-                        ((Rs1 | ~val2) & 0x1))<63:>}},
-                    {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
-                );//SUBcc
-                0x15: andncc({{
-                    int64_t val2 = (I ? SIMM13.sdw : Rs2);
-                    Rd = Rs1 & ~val2;}},
-                    {{0}},{{0}},{{0}},{{0}});//ANDNcc
-                0x16: orncc({{
-                    int64_t val2 = (I ? SIMM13.sdw : Rs2);
-                    Rd = Rs1 | ~val2;}},
-                    {{0}},{{0}},{{0}},{{0}});//ORNcc
-                0x17: xnorcc({{
-                    int64_t val2 = (I ? SIMM13.sdw : Rs2);
-                    Rd = ~(Rs1 ^ val2);}},
-                    {{0}},{{0}},{{0}},{{0}});//XNORcc
-                0x18: addccc({{
-                    int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
-                    int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
-                    Rd = resTemp = Rs1 + val2 + carryin;}},
-                    {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31
-                        + carryin)}},
-                    {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
-                    {{((Rs1 >> 1) + (val2 >> 1) +
-                        ((Rs1 & val2) | (carryin & (Rs1 | val2)) & 0x1))<63:>}},
-                    {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
-                );//ADDCcc
-                0x1A: umulcc({{
-                    uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
-                    Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
-                    xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}},
-                    {{0}},{{0}},{{0}},{{0}});//UMULcc
-                        0x1B: smulcc({{
-                                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
-                                Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>;
-                                xc->regs.MiscRegs.yFields.value = resTemp<63:32>;}}
-                        ,{{0}},{{0}},{{0}},{{0}});//SMULcc
-                        0x1C: subccc({{
-                                int64_t resTemp, val2 = (int64_t)(I ? SIMM13.sdw : Rs2);
-                                int64_t carryin = xc->regs.MiscRegs.ccrfields.iccfields.c;
-                                Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
-                                {{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}},
-                                {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
-                                {{((Rs1 >> 1) + (~(val2 + carryin)) >> 1) + ((Rs1 | ~(val2+carryin)) & 0x1))<63:>}},
-                                {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
-                        );//SUBCcc
-                        0x1D: udivxcc({{
-                                uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
-                                if(val2 == 0) throw division_by_zero;
-                                Rd.udw = Rs1.udw / val2;}}
-                        ,{{0}},{{0}},{{0}},{{0}});//UDIVXcc
-                        0x1E: udivcc({{
-                                uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
-                                if(val2 == 0) throw division_by_zero;
-                                resTemp = (uint64_t)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.udw<31:0>) / val2;
-                                int32_t overflow = (resTemp<63:32> != 0);
-                                if(overflow) rd.udw = resTemp = 0xFFFFFFFF;
-                                else rd.udw = resTemp;}},
-                                {{0}},
-                                {{overflow}},
-                                {{0}},
-                                {{0}}
-                        );//UDIVcc
-                        0x1F: sdivcc({{
-                                int32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
-                                if(val2 == 0) throw division_by_zero;
-                                Rd.sdw = resTemp = (int64_t)((xc->regs.MiscRegs.yFields.value << 32) | Rs1.sdw<31:0>) / val2;
-                                int32_t overflow = (resTemp<63:31> != 0);
-                                int32_t underflow = (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
-                                if(overflow) rd.udw = resTemp = 0x7FFFFFFF;
-                                else if(underflow) rd.udw = resTemp = 0xFFFFFFFF80000000;
-                                else rd.udw = resTemp;}},
-                                {{0}},
-                                {{overflow || underflow}},
-                                {{0}},
-                                {{0}}
-                        );//SDIVcc
-                        0x20: taddcc({{
-                                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
-                                Rd = resTemp = Rs1 + val2;
-                                int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
-                                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
-                                {{overflow}},
-                                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
-                                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
-                        );//TADDcc
-                        0x21: tsubcc({{
-                                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
-                                Rd = resTemp = Rs1 + val2;
-                                int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
-                                {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
-                                {{overflow}},
-                                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
-                                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
-                        );//TSUBcc
-                        0x22: taddcctv({{
-                                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
-                                Rd = resTemp = Rs1 + val2;
-                                int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
-                                if(overflow) throw tag_overflow;}},
-                                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
-                                {{overflow}},
-                                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
-                                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
-                        );//TADDccTV
-                        0x23: tsubcctv({{
-                                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
-                                Rd = resTemp = Rs1 + val2;
-                                int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
-                                if(overflow) throw tag_overflow;}},
-                                {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
-                                {{overflow}},
-                                {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
-                                {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
-                        );//TSUBccTV
-                        0x24: mulscc({{
-                                int64_t resTemp, multiplicand = (I ? SIMM13.sdw : Rs2);
-                                int32_t multiplier = Rs1<31:0>;
-                                int32_t savedLSB = Rs1<0:>;
-                                multiplier = multipler<31:1> |
-                                        ((xc->regs.MiscRegs.ccrFields.iccFields.n
-                                        ^ xc->regs.MiscRegs.ccrFields.iccFields.v) << 32);
-                                if(!xc->regs.MiscRegs.yFields.value<0:>)
-                                        multiplicand = 0;
-                                Rd = resTemp = multiplicand + multiplier;
-                                xc->regs.MiscRegs.yFields.value = xc->regs.MiscRegs.yFields.value<31:1> | (savedLSB << 31);}},
-                                {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
-                                {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
-                                {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
-                                {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
-                        );//MULScc
+            format IntegerOp
+            {
+                0x25: decode X {
+                        0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); //SLL
+                        0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); //SLLX
                 }
-                format IntegerOp
-                {
-                        0x25: decode X {
-                                0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); //SLL
-                                0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); //SLLX
-                        }
-                        0x26: decode X {
-                                0x0: srl({{Rd = Rs1.udw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRL
-                                0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRLX
-                        }
-                        0x27: decode X {
-                                0x0: sra({{Rd = Rs1.sdw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRA
-                                0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRAX
-                        }
-                        0x28: decode RS1 {
-                                0x0: rdy({{Rd = xc->regs.MiscRegs.yFields.value;}}); //RDY
-                                0x2: rdccr({{Rd = xc->regs.MiscRegs.ccr;}}); //RDCCR
-                                0x3: rdasi({{Rd = xc->regs.MiscRegs.asi;}}); //RDASI
-                                0x4: rdtick({{
-                                        if(xc->regs.MiscRegs.pstateFields.priv == 0 &&
-                                                xc->regs.MiscRegs.tickFields.npt == 1)
-                                                throw privileged_action;
-                                        Rd = xc->regs.MiscRegs.tick;
-                                }});//RDTICK
-                                0x5: rdpc({{Rd = xc->regs.pc;}}); //RDPC
-                                0x6: rdfprs({{Rd = xc->regs.MiscRegs.fprs;}}); //RDFPRS
-                                0xF: decode I {
-                                        0x0: Noop::membar({{//Membar isn't needed yet}}); //MEMBAR
-                                        0x1: Noop::stbar({{//Stbar isn/'t needed yet}}); //STBAR
-                                }
-                        }
-
-                        0x2A: decode RS1 {
-                                0x0: rdprtpc({{checkPriv Rd = xc->regs.MiscRegs.tpc[xc->regs.MiscRegs.tl];}});
-                                0x1: rdprtnpc({{checkPriv Rd = xc->regs.MiscRegs.tnpc[xc->regs.MiscRegs.tl];}});
-                                0x2: rdprtstate({{checkPriv Rd = xc->regs.MiscRegs.tstate[xc->regs.MiscRegs.tl];}});
-                                0x3: rdprtt({{checkPriv Rd = xc->regs.MiscRegs.tt[xc->regs.MiscRegs.tl];}});
-                                0x4: rdprtick({{checkPriv Rd = xc->regs.MiscRegs.tick;}});
-                                0x5: rdprtba({{checkPriv Rd = xc->regs.MiscRegs.tba;}});
-                                0x6: rdprpstate({{checkPriv Rd = xc->regs.MiscRegs.pstate;}});
-                                0x7: rdprtl({{checkPriv Rd = xc->regs.MiscRegs.tl;}});
-                                0x8: rdprpil({{checkPriv Rd = xc->regs.MiscRegs.pil;}});
-                                0x9: rdprcwp({{checkPriv Rd = xc->regs.MiscRegs.cwp;}});
-                                0xA: rdprcansave({{checkPriv Rd = xc->regs.MiscRegs.cansave;}});
-                                0xB: rdprcanrestore({{checkPriv Rd = xc->regs.MiscRegs.canrestore;}});
-                                0xC: rdprcleanwin({{checkPriv Rd = xc->regs.MiscRegs.cleanwin;}});
-                                0xD: rdprotherwin({{checkPriv Rd = xc->regs.MiscRegs.otherwin;}});
-                                0xE: rdprwstate({{checkPriv Rd = xc->regs.MiscRegs.wstate;}});
-                                0xF: rdprfq({{throw illegal_instruction;}}); //The floating point queue isn't implemented right now.
-                        }
-                        0x2B: BasicOperate::flushw({{\\window toilet}}); //FLUSHW
-                        0x2C: movcc({{
-                                ccBank = (CC24 << 2) | (CC14 << 1) | (CC04 << 0);
-                                switch(ccBank)
-                                {
-                                        case 0: case 1: case 2: case 3:
-                                                throw fp_disabled;
-                                        break;
-                                        case 5: case 7:
-                                                throw illegal_instruction;
-                                        break;
-                                        case 4:
-                                                if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, COND4))
-                                                        Rd = (I ? SIMM11.sdw : RS2);
-                                        break;
-                                        case 6:
-                                                if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, COND4))
-                                                        Rd = (I ? SIMM11.sdw : RS2);
-                                        break;
-                                }
-                        }});//MOVcc
-                        0x2D: sdivx({{
-                                int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                if(val2 == 0) throw division_by_zero;
-                                Rd.sdw = Rs1.sdw / val2;
-                        }});//SDIVX
-                        0x2E: decode RS1 {
-                                0x0: IntegerOp::popc({{
-                                int64_t count = 0, val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}
-                                for(unsigned int x = 0; x < 16; x++)
-                                {
-                                        count += oneBits[val2 & 0xF];
-                                        val2 >> 4;
-                                }
-                                }});//POPC
-                        }
-                        0x2F: movr({{
-                                uint64_t val2 = (I ? SIMM10.sdw : Rs2.sdw);
-                                switch(RCOND)
-                                {
-                                        case 0: case 4:
-                                                throw illegal_instruction;
-                                        break;
-                                        case 1:
-                                                if(Rs1 == 0) Rd = val2;
-                                        break;
-                                        case 2:
-                                                if(Rs1 <= 0) Rd = val2;
-                                        break;
-                                        case 3:
-                                                if(Rs1 = 0) Rd = val2;
-                                        break;
-                                        case 5:
-                                                if(Rs1 != 0) Rd = val2;
-                                        break;
-                                        case 6:
-                                                if(Rs1 > 0) Rd = val2;
-                                        break;
-                                        case 7:
-                                                if(Rs1 >= 0) Rd = val2;
-                                        break;
-                                }
-                        }});//MOVR
-                        0x30: decode RD {
-                                0x0: wry({{
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.y = Rs1 ^ val2;
-                                }});//WRY
-                                0x2: wrccr({{
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.ccr = Rs1 ^ val2;
-                                }});//WRCCR
-                                0x3: wrasi({{
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.asi = Rs1 ^ val2;
-                                }});//WRASI
-                                0x6: wrfprs({{
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.asi = Rs1 ^ val2;
-                                }});//WRFPRS
-                                0xF: Trap::sir({{software_initiated_reset}}); //SIR
+                0x26: decode X {
+                        0x0: srl({{Rd = Rs1.udw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRL
+                        0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRLX
+                }
+                0x27: decode X {
+                        0x0: sra({{Rd = Rs1.sdw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRA
+                        0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRAX
+                }
+                0x28: decode RS1 {
+                        0x0: rdy({{Rd = YValue;}}); //RDY
+                        0x2: rdccr({{Rd = Ccr;}}); //RDCCR
+                        0x3: rdasi({{Rd = Asi;}}); //RDASI
+                        0x4: PrivTick::rdtick({{Rd = Tick;}});
+                        0x5: rdpc({{Rd = xc->regs.pc;}}); //RDPC
+                        0x6: rdfprs({{Rd = Fprs;}}); //RDFPRS
+                        0xF: decode I {
+                            0x0: Noop::membar({{//Membar isn't needed yet}});
+                            0x1: Noop::stbar({{//Stbar isn't needed yet}});
                         }
-                        0x31: decode FCN {
-                                0x0: BasicOperate::saved({{\\Boogy Boogy}}); //SAVED
-                                0x1: BasicOperate::restored({{\\Boogy Boogy}}); //RESTORED
+                }
+                0x2A: decode RS1 {
+                    format Priv
+                    {
+                        0x0: rdprtpc({{
+                            Rd = xc->readMiscReg(MISCREG_TPC_BASE + tl);
+                            }});
+                        0x1: rdprtnpc({{
+                            Rd = xc->readMiscReg(MISCREG_TNPC_BASE + tl);
+                            }});
+                        0x2: rdprtstate({{
+                            Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + tl);
+                            }});
+                        0x3: rdprtt({{
+                            Rd = xc->readMiscReg(MISCREG_TT_BASE + tl);
+                            }});
+                        0x4: rdprtick({{Rd = Tick;}});
+                        0x5: rdprtba({{Rd = Tba;}});
+                        0x6: rdprpstate({{Rd = Pstate;}});
+                        0x7: rdprtl({{Rd = Tl;}});
+                        0x8: rdprpil({{Rd = Pil;}});
+                        0x9: rdprcwp({{Rd = Cwp;}});
+                        0xA: rdprcansave({{Rd = Cansave;}});
+                        0xB: rdprcanrestore({{Rd = CanRestore;}});
+                        0xC: rdprcleanwin({{Rd = Cleanwin;}});
+                        0xD: rdprotherwin({{Rd = Otherwin;}});
+                        0xE: rdprwstate({{Rd = Wstate;}});
+                    }
+                    //The floating point queue isn't implemented right now.
+                    0xF: Trap::rdprfq({{fault = IllegalInstruction;}});
+                    0x1F: Priv::rdprver({{Rd = Ver;}});
+                }
+                0x2B: BasicOperate::flushw({{\\window toilet}}); //FLUSHW
+                0x2C: movcc({{
+                        ccBank = (CC24 << 2) | (CC14 << 1) | (CC04 << 0);
+                        switch(ccBank)
+                        {
+                                case 0: case 1: case 2: case 3:
+                                        fault = new FpDisabled;
+                                break;
+                                case 5: case 7:
+                                        fault = new IllegalInstruction;
+                                break;
+                                case 4:
+                                        if(passesCondition(CcrIcc, COND4))
+                                                Rd = (I ? SIMM11.sdw : RS2);
+                                break;
+                                case 6:
+                                        if(passesCondition(CcrXcc, COND4))
+                                                Rd = (I ? SIMM11.sdw : RS2);
+                                break;
                         }
-                        0x32: decode RD {
-                                0x0: wrprtpc({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.tpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
-                                }});
-                                0x1: wrprtnpc({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.tnpc[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
-                                }});
-                                0x2: wrprtstate({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.tstate[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
-                                }});
-                                0x3: wrprtt({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.tt[xc->regs.MiscRegs.tl] = Rs1 ^ val2;
-                                }});
-                                0x4: wrprtick({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.tick = Rs1 ^ val2;
-                                }});
-                                0x5: wrprtba({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.tba = Rs1 ^ val2;
-                                }});
-                                0x6: wrprpstate({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.pstate = Rs1 ^ val2;
-                                }});
-                                0x7: wrprtl({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.tl = Rs1 ^ val2;
-                                }});
-                                0x8: wrprpil({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.pil = Rs1 ^ val2;
-                                }});
-                                0x9: wrprcwp({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.cwp = Rs1 ^ val2;
-                                }});
-                                0xA: wrprcansave({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.cansave = Rs1 ^ val2;
-                                }});
-                                0xB: wrprcanrestore({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.canrestore = Rs1 ^ val2;
-                                }});
-                                0xC: wrprcleanwin({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.cleanwin = Rs1 ^ val2;
-                                }});
-                                0xD: wrprotherwin({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.otherwin = Rs1 ^ val2;
-                                }});
-                                0xE: wrprwstate({{checkPriv
-                                        uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                        xc->regs.MiscRegs.wstate = Rs1 ^ val2;
-                                }});
-                        }
-
-                        0x34: Trap::fpop1({{Throw fp_disabled;}}); //FPOP1
-                        0x35: Trap::fpop2({{Throw fp_disabled;}}); //FPOP2
-
-
-                        0x38: Branch::jmpl({{//Stuff}}); //JMPL
-                        0x39: Branch::return({{//Other Stuff}}); //RETURN
-                        0x3A: Trap::tcc({{
-                                switch((CC14 << 1) | (CC04 << 0))
-                                {
-                                        case 1: case 3:
-                                                throw illegal_instruction;
-                                        case 0:
-#if FULL_SYSTEM
-                                                throw trap_instruction;
-#else
-                                                if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, machInst<25:28>))
-                                                    // At least glibc only uses trap 0,
-                                                    // solaris/sunos may use others
-                                                    assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0);
-                                                    xc->syscall();
-#endif
-                                        break;
-                                        case 2:
-#if FULL_SYSTEM
-                                                throw trap_instruction;
-#else
-                                                if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, machInst<25:28>))
-                                                    // At least glibc only uses trap 0,
-                                                    // solaris/sunos may use others
-                                                    assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0);
-                                                    xc->syscall();
-#endif
-                                        break;
-                                }
-                        }}); //Tcc
-                        0x3B: BasicOperate::flush({{//Lala}}); //FLUSH
-                        0x3C: BasicOperate::save({{//leprechauns); //SAVE
-                        0x3D: BasicOperate::restore({{//Eat my short int}}); //RESTORE
-                        0x3E: decode FCN {
-                                0x1: BasicOperate::done({{//Done thing}}); //DONE
-                                0x2: BasicOperate::retry({{//Retry thing}}); //RETRY
+                }});//MOVcc
+                0x2D: sdivx({{
+                        int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                        if(val2 == 0) fault = new DivisionByZero;
+                        else Rd.sdw = Rs1.sdw / val2;
+                }});//SDIVX
+                0x2E: decode RS1 {
+                        0x0: IntegerOp::popc({{
+                        int64_t count = 0, val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                        uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}
+                        for(unsigned int x = 0; x < 16; x++)
+                        {
+                                count += oneBits[val2 & 0xF];
+                                val2 >> 4;
                         }
+                        }});//POPC
                 }
-        }
-        0x3: decode OP3 {
-                format Mem {
-                        0x00: lduw({{Rd.uw = Mem.uw;}}); //LDUW
-                        0x01: ldub({{Rd.ub = Mem.ub;}}); //LDUB
-                        0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH
-                        0x03: ldd({{
-                                uint64_t val = Mem.udw;
-                                setIntReg(RD & (~1), val<31:0>);
-                                setIntReg(RD | 1, val<63:32>);
-                        }});//LDD
-                        0x04: stw({{Mem.sw = Rd.sw;}}); //STW
-                        0x05: stb({{Mem.sb = Rd.sb;}}); //STB
-                        0x06: sth({{Mem.shw = Rd.shw;}}); //STH
-                        0x07: std({{
-                                Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
-                        }});//STD
-                        0x08: ldsw({{Rd.sw = Mem.sw;}}); //LDSW
-                        0x09: ldsb({{Rd.sb = Mem.sb;}}); //LDSB
-                        0x0A: ldsh({{Rd.shw = Mem.shw;}}); //LDSH
-                        0x0B: ldx({{Rd.udw = Mem.udw;}}); //LDX
-
-                        0x0D: ldstub({{
-                                Rd.ub = Mem.ub;
-                                Mem.ub = 0xFF;
-                        }}); //LDSTUB
-                        0x0E: stx({{Rd.udw = Mem.udw;}}); //STX
-                        0x0F: swap({{
-                                uint32_t temp = Rd.uw;
-                                Rd.uw = Mem.uw;
-                                Mem.uw = temp;
-                        }}); //SWAP
-                        0x10: lduwa({{Rd.uw = Mem.uw;}}); //LDUWA
-                        0x11: lduba({{Rd.ub = Mem.ub;}}); //LDUBA
-                        0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA
-                        0x13: ldda({{
-                                uint64_t val = Mem.udw;
-                                setIntReg(RD & (~1), val<31:0>);
-                                setIntReg(RD | 1, val<63:32>);
-                        }}); //LDDA
-                        0x14: stwa({{Mem.uw = Rd.uw;}}); //STWA
-                        0x15: stba({{Mem.ub = Rd.ub;}}); //STBA
-                        0x16: stha({{Mem.uhw = Rd.uhw;}}); //STHA
-                        0x17: stda({{
-                                Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
-                        }}); //STDA
-                        0x18: ldswa({{Rd.sw = Mem.sw;}}); //LDSWA
-                        0x19: ldsba({{Rd.sb = Mem.sb;}}); //LDSBA
-                        0x1A: ldsha({{Rd.shw = Mem.shw;}}); //LDSHA
-                        0x1B: ldxa({{Rd.sdw = Mem.sdw;}}); //LDXA
-
-                        0x1D: ldstuba({{
-                                Rd.ub = Mem.ub;
-                                Mem.ub = 0xFF;
-                        }}); //LDSTUBA
-                        0x1E: stxa({{Mem.sdw = Rd.sdw}}); //STXA
-                        0x1F: swapa({{
-                                uint32_t temp = Rd.uw;
-                                Rd.uw = Mem.uw;
-                                Mem.uw = temp;
-                        }}); //SWAPA
-                        0x20: Trap::ldf({{throw fp_disabled;}}); //LDF
-                        0x21: decode X {
-                                0x0: Trap::ldfsr({{throw fp_disabled;}}); //LDFSR
-                                0x1: Trap::ldxfsr({{throw fp_disabled;}}); //LDXFSR
-                        }
-                        0x22: Trap::ldqf({{throw fp_disabled;}}); //LDQF
-                        0x23: Trap::lddf({{throw fp_disabled;}}); //LDDF
-                        0x24: Trap::stf({{throw fp_disabled;}}); //STF
-                        0x25: decode X {
-                                0x0: Trap::stfsr({{throw fp_disabled;}}); //STFSR
-                                0x1: Trap::stxfsr({{throw fp_disabled;}}); //STXFSR
+                0x2F: movr({{
+                        uint64_t val2 = (I ? SIMM10.sdw : Rs2.sdw);
+                        switch(RCOND3)
+                        {
+                                case 0: case 4:
+                                        fault = IllegalInstruction;
+                                break;
+                                case 1:
+                                        if(Rs1 == 0) Rd = val2;
+                                break;
+                                case 2:
+                                        if(Rs1 <= 0) Rd = val2;
+                                break;
+                                case 3:
+                                        if(Rs1 = 0) Rd = val2;
+                                break;
+                                case 5:
+                                        if(Rs1 != 0) Rd = val2;
+                                break;
+                                case 6:
+                                        if(Rs1 > 0) Rd = val2;
+                                break;
+                                case 7:
+                                        if(Rs1 >= 0) Rd = val2;
+                                break;
                         }
-                        0x26: Trap::stqf({{throw fp_disabled;}}); //STQF
-                        0x27: Trap::stdf({{throw fp_disabled;}}); //STDF
-
-
-
-
+                }});//MOVR
+                0x30: decode RD {
+                        0x0: wry({{
+                                uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                Y = Rs1 ^ val2;
+                        }});//WRY
+                        0x2: wrccr({{
+                                uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                Ccr = Rs1 ^ val2;
+                        }});//WRCCR
+                        0x3: wrasi({{
+                                uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                Asi = Rs1 ^ val2;
+                        }});//WRASI
+                        0x6: wrfprs({{
+                                uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
+                                Asi = Rs1 ^ val2;
+                        }});//WRFPRS
+                        0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}});
+                }
+                0x31: decode FCN {
+                        0x0: BasicOperate::saved({{\\Boogy Boogy}}); //SAVED
+                        0x1: BasicOperate::restored({{\\Boogy Boogy}}); //RESTORED
+                }
+                0x32: decode RD {
+                    format Priv
+                    {
+                        0x0: wrprtpc({{
+                            xc->setMiscReg(MISCREG_TPC_BASE + tl,
+                                Rs1 ^ Rs2_or_imm13);
+                        }});
+                        0x1: wrprtnpc({{
+                            xc->setMiscReg(MISCREG_TNPC_BASE + tl,
+                                Rs1 ^ Rs2_or_imm13);
+                        }});
+                        0x2: wrprtstate({{
+                            xc->setMiscReg(MISCREG_TSTATE_BASE + tl,
+                                Rs1 ^ Rs2_or_imm13);
+                        }});
+                        0x3: wrprtt({{
+                            xc->setMiscReg(MISCREG_TT_BASE + tl,
+                                Rs1 ^ Rs2_or_imm13);
+                        }});
+                        0x4: wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
+                        0x5: wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
+                        0x6: wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
+                        0x7: wrprtl({{Tl = Rs1 ^ Rs2_or_imm13;}});
+                        0x8: wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
+                        0x9: wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
+                        0xA: wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
+                        0xB: wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
+                        0xC: wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
+                        0xD: wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
+                        0xE: wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
+                    }
+                }
 
-                        0x2D: Noop::prefetch({{ }}); //PREFETCH
+                0x34: Trap::fpop1({{fault = new FpDisabled;}});
+                0x35: Trap::fpop2({{fault = new FpDisabled;}});
 
 
-                        0x30: Trap::ldfa({{throw fp_disabled;}}); //LDFA
+                0x38: Branch::jmpl({{//Stuff}}); //JMPL
+                0x39: Branch::return({{//Other Stuff}}); //RETURN
+                0x3A: decode CC04
+                {
+                    // If CC04 == 1, it's an illegal instruction
+                    0x0: decode CC14
+                    {
+                        0x0: Trap::tcci({{
+                            if(passesCondition(ccr_icc, machInst<25:28>))
+                                fault = new TrapInstruction;
+                        }});
+                        0x1: Trap::tccx({{
+                            if(passesCondition(ccr_xcc, machInst<25:28>))
+                                fault = new TrapInstruction;
+                        }});
+                    }
+                }
+                0x3B: BasicOperate::flush({{//Lala}}); //FLUSH
+                0x3C: BasicOperate::save({{//leprechauns); //SAVE
+                0x3D: BasicOperate::restore({{//Eat my short int}}); //RESTORE
+                0x3E: decode FCN {
+                        0x1: BasicOperate::done({{//Done thing}}); //DONE
+                        0x2: BasicOperate::retry({{//Retry thing}}); //RETRY
+                }
+            }
+    }
+    0x3: decode OP3 {
+            format Mem {
+                    0x00: lduw({{Rd.uw = Mem.uw;}}); //LDUW
+                    0x01: ldub({{Rd.ub = Mem.ub;}}); //LDUB
+                    0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH
+                    0x03: ldd({{
+                            uint64_t val = Mem.udw;
+                            setIntReg(RD & (~1), val<31:0>);
+                            setIntReg(RD | 1, val<63:32>);
+                    }});//LDD
+                    0x04: stw({{Mem.sw = Rd.sw;}}); //STW
+                    0x05: stb({{Mem.sb = Rd.sb;}}); //STB
+                    0x06: sth({{Mem.shw = Rd.shw;}}); //STH
+                    0x07: std({{
+                            Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
+                    }});//STD
+                    0x08: ldsw({{Rd.sw = Mem.sw;}}); //LDSW
+                    0x09: ldsb({{Rd.sb = Mem.sb;}}); //LDSB
+                    0x0A: ldsh({{Rd.shw = Mem.shw;}}); //LDSH
+                    0x0B: ldx({{Rd.udw = Mem.udw;}}); //LDX
 
-                        0x32: Trap::ldqfa({{throw fp_disabled;}}); //LDQFA
-                        0x33: Trap::lddfa({{throw fp_disabled;}}); //LDDFA
-                        0x34: Trap::stfa({{throw fp_disabled;}}); //STFA
-                        0x35: Trap::stqfa({{throw fp_disabled;}}); //STQFA
-                        0x36: Trap::stdfa({{throw fp_disabled;}}); //STDFA
+                    0x0D: ldstub({{
+                            Rd.ub = Mem.ub;
+                            Mem.ub = 0xFF;
+                    }}); //LDSTUB
+                    0x0E: stx({{Rd.udw = Mem.udw;}}); //STX
+                    0x0F: swap({{
+                            uint32_t temp = Rd.uw;
+                            Rd.uw = Mem.uw;
+                            Mem.uw = temp;
+                    }}); //SWAP
+                    0x10: lduwa({{Rd.uw = Mem.uw;}}); //LDUWA
+                    0x11: lduba({{Rd.ub = Mem.ub;}}); //LDUBA
+                    0x12: lduha({{Rd.uhw = Mem.uhw;}}); //LDUHA
+                    0x13: ldda({{
+                            uint64_t val = Mem.udw;
+                            setIntReg(RD & (~1), val<31:0>);
+                            setIntReg(RD | 1, val<63:32>);
+                    }}); //LDDA
+                    0x14: stwa({{Mem.uw = Rd.uw;}}); //STWA
+                    0x15: stba({{Mem.ub = Rd.ub;}}); //STBA
+                    0x16: stha({{Mem.uhw = Rd.uhw;}}); //STHA
+                    0x17: stda({{
+                            Mem.udw = readIntReg(RD & (~1))<31:0> | (readIntReg(RD | 1)<31:0> << 32);
+                    }}); //STDA
+                    0x18: ldswa({{Rd.sw = Mem.sw;}}); //LDSWA
+                    0x19: ldsba({{Rd.sb = Mem.sb;}}); //LDSBA
+                    0x1A: ldsha({{Rd.shw = Mem.shw;}}); //LDSHA
+                    0x1B: ldxa({{Rd.sdw = Mem.sdw;}}); //LDXA
 
+                    0x1D: ldstuba({{
+                            Rd.ub = Mem.ub;
+                            Mem.ub = 0xFF;
+                    }}); //LDSTUBA
+                    0x1E: stxa({{Mem.sdw = Rd.sdw}}); //STXA
+                    0x1F: swapa({{
+                            uint32_t temp = Rd.uw;
+                            Rd.uw = Mem.uw;
+                            Mem.uw = temp;
+                    }}); //SWAPA
+                    0x20: Trap::ldf({{fault = new FpDisabled;}});
+                    0x21: decode X {
+                        0x0: Trap::ldfsr({{fault = new FpDisabled;}});
+                        0x1: Trap::ldxfsr({{fault = new FpDisabled;}});
+                    }
+                    0x22: Trap::ldqf({{fault = new FpDisabled;}});
+                    0x23: Trap::lddf({{fault = new FpDisabled;}});
+                    0x24: Trap::stf({{fault = new FpDisabled;}});
+                    0x25: decode X {
+                        0x0: Trap::stfsr({{fault = new FpDisabled;}});
+                        0x1: Trap::stxfsr({{fault = new FpDisabled;}});
+                    }
+                    0x26: Trap::stqf({{fault = new FpDisabled;}});
+                    0x27: Trap::stdf({{fault = new FpDisabled;}});
 
+                    0x2D: Noop::prefetch({{ }}); //PREFETCH
 
+                    0x30: Trap::ldfa({{return new FpDisabled;}});
 
+                    0x32: Trap::ldqfa({{fault = new FpDisabled;}});
+                    0x33: Trap::lddfa({{fault = new FpDisabled;}});
+                    0x34: Trap::stfa({{fault = new FpDisabled;}});
+                    0x35: Trap::stqfa({{fault = new FpDisabled;}});
+                    0x36: Trap::stdfa({{fault = new FpDisabled;}});
 
-                        0x3C: Cas::casa(
-                                {{uint64_t val = Mem.uw;
-                                if(Rs2.uw == val)
-                                        Mem.uw = Rd.uw;
-                                Rd.uw = val;
-                        }}); //CASA
-                        0x3D: Noop::prefetcha({{ }}); //PREFETCHA
-                        0x3E: Cas::casxa(
-                                {{uint64_t val = Mem.udw;
-                                if(Rs2 == val)
-                                        Mem.udw = Rd;
-                                Rd = val;
-                        }}); //CASXA
-                }
-        }
+                    0x3C: Cas::casa(
+                            {{uint64_t val = Mem.uw;
+                            if(Rs2.uw == val)
+                                    Mem.uw = Rd.uw;
+                            Rd.uw = val;
+                    }}); //CASA
+                    0x3D: Noop::prefetcha({{ }}); //PREFETCHA
+                    0x3E: Cas::casxa(
+                            {{uint64_t val = Mem.udw;
+                            if(Rs2 == val)
+                                    Mem.udw = Rd;
+                            Rd = val;
+                    }}); //CASXA
+            }
+    }
 }
diff --git a/arch/sparc/isa/formats.isa b/arch/sparc/isa/formats.isa
index 547f8be48..9310ba3d3 100644
--- a/arch/sparc/isa/formats.isa
+++ b/arch/sparc/isa/formats.isa
@@ -5,12 +5,21 @@
 //Include the integerOp and integerOpCc format
 ##include "m5/arch/sparc/isa/formats/integerop.isa"
 
-//Include the mem format
+//Include the memory format
 ##include "m5/arch/sparc/isa/formats/mem.isa"
 
+//Include the compare and swap format
+##include "m5/arch/sparc/isa/formats/cas.isa"
+
 //Include the trap format
 ##include "m5/arch/sparc/isa/formats/trap.isa"
 
+//Include the "unknown" format
+##include "m5/arch/sparc/isa/formats/unknown.isa"
+
+//Include the priveleged mode format
+##include "m5/arch/sparc/isa/formats/priv.isa"
+
 //Include the branch format
 ##include "m5/arch/sparc/isa/formats/branch.isa"
 
diff --git a/arch/sparc/isa/formats/branch.isa b/arch/sparc/isa/formats/branch.isa
index 80101de1b..b9dc960de 100644
--- a/arch/sparc/isa/formats/branch.isa
+++ b/arch/sparc/isa/formats/branch.isa
@@ -34,7 +34,6 @@ def template BranchExecute {{
         {
             //Attempt to execute the instruction
             Fault fault = NoFault;
-            checkPriv;
 
             %(op_decl)s;
             %(op_rd)s;
@@ -57,6 +56,6 @@ def format Branch(code, *opt_flags) {{
         iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        decode_block = BasicDecode.subst(iop)
         exec_output = BranchExecute.subst(iop)
 }};
diff --git a/arch/sparc/isa/formats/integerop.isa b/arch/sparc/isa/formats/integerop.isa
index 5a9e09896..7b6bfa54d 100644
--- a/arch/sparc/isa/formats/integerop.isa
+++ b/arch/sparc/isa/formats/integerop.isa
@@ -11,13 +11,13 @@ output header {{
         {
           protected:
             // Constructor
-            IntegerOp(const char *mnem, MachInst _machInst, OpClass __opClass) :
+            IntegerOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
                 SparcStaticInst(mnem, _machInst, __opClass)
             {
             }
 
             std::string generateDisassembly(Addr pc,
-                    const SymbolTable *symtab) const;
+                const SymbolTable *symtab) const;
         };
 }};
 
@@ -25,49 +25,40 @@ output decoder {{
         std::string IntegerOp::generateDisassembly(Addr pc,
                 const SymbolTable *symtab) const
         {
-                return "Integer instruction\n";
+            return "Integer instruction\n";
         }
 }};
 
 def template IntegerExecute {{
-        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+                Trace::InstRecord *traceData) const
         {
-                //These are set to constants when the execute method
-                //is generated
-                bool useCc = ;
-                bool checkPriv = ;
+            Fault fault;
+            //These are set to constants when the execute method
+            //is generated
+            bool useCc = ;
 
-                //Attempt to execute the instruction
-                try
-                {
-                        checkPriv;
+            %(op_decl)s;
+            %(op_rd)s;
+            %(code)s;
 
-                        %(op_decl)s;
-                        %(op_rd)s;
-                        %(code)s;
-                }
-                //If we have an exception for some reason,
-                //deal with it
-                catch(SparcException except)
-                {
-                        //Deal with exception
-                        return No_Fault;
-                }
-
-                //Write the resulting state to the execution context
+            //Write the resulting state to the execution context
+            if(fault == NoFault)
+            {
                 %(op_wb)s;
                 if(useCc)
                 {
-                        xc->regs.miscRegFile.ccrFields.iccFields.n = Rd & (1 << 63);
-                        xc->regs.miscRegFile.ccrFields.iccFields.z = (Rd == 0);
-                        xc->regs.miscRegFile.ccrFields.iccFields.v = ivValue;
-                        xc->regs.miscRegFile.ccrFields.iccFields.c = icValue;
-                        xc->regs.miscRegFile.ccrFields.xccFields.n = Rd & (1 << 31);
-                        xc->regs.miscRegFile.ccrFields.xccFields.z = ((Rd & 0xFFFFFFFF) == 0);
-                        xc->regs.miscRegFile.ccrFields.xccFields.v = xvValue;
-                        xc->regs.miscRegFile.ccrFields.xccFields.c = xcValue;
+                    CcrIccN = Rd & (1 << 63);
+                    CcrIccZ = (Rd == 0);
+                    CcrIccV = ivValue;
+                    CcrIccC = icValue;
+                    CcrXccN = Rd & (1 << 31);
+                    CcrXccZ = ((Rd & 0xFFFFFFFF) == 0);
+                    CcrXccV = xvValue;
+                    CcrXccC = xcValue;
                 }
-                return No_Fault;
+            }
+            return fault;
         }
 }};
 
@@ -75,19 +66,13 @@ def template IntegerExecute {{
 def format IntegerOp(code, *opt_flags) {{
         orig_code = code
         cblk = CodeBlock(code)
-        checkPriv = (code.find('checkPriv') != -1)
-        code.replace('checkPriv', '')
-        if checkPriv:
-                code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
-        else:
-                code.replace('checkPriv;', '')
         for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
                        ('xvValue', '0'), ('xcValue', '0')):
                 code.replace(marker, value)
         iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        decode_block = BasicDecode.subst(iop)
         exec_output = IntegerExecute.subst(iop)
 }};
 
@@ -95,18 +80,12 @@ def format IntegerOp(code, *opt_flags) {{
 def format IntegerOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
         orig_code = code
         cblk = CodeBlock(code)
-        checkPriv = (code.find('checkPriv') != -1)
-        code.replace('checkPriv', '')
-        if checkPriv:
-                code.replace('checkPriv;', 'if(!xc->regs.miscRegFile.pstateFields.priv) throw privileged_opcode;')
-        else:
-                code.replace('checkPriv;', '')
         for (marker, value) in (('ivValue', ivValue), ('icValue', icValue),
                        ('xvValue', xvValue), ('xcValue', xcValue)):
                 code.replace(marker, value)
         iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        decode_block = BasicDecode.subst(iop)
         exec_output = IntegerExecute.subst(iop)
 }};
diff --git a/arch/sparc/isa/formats/mem.isa b/arch/sparc/isa/formats/mem.isa
index d72de47d0..06725eae8 100644
--- a/arch/sparc/isa/formats/mem.isa
+++ b/arch/sparc/isa/formats/mem.isa
@@ -12,7 +12,7 @@ output header {{
           protected:
 
             // Constructor
-            Mem(const char *mnem, MachInst _machInst, OpClass __opClass) :
+            Mem(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
                 SparcStaticInst(mnem, _machInst, __opClass)
             {
             }
@@ -56,18 +56,7 @@ def format Mem(code, *opt_flags) {{
         iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        decode_block = BasicDecode.subst(iop)
         exec_output = MemExecute.subst(iop)
         exec_output.replace('ea_code', 'EA = I ? (R1 + SIMM13) : R1 + R2;');
 }};
-
-def format Cas(code, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
-        exec_output = MemExecute.subst(iop)
-        exec_output.replace('ea_code', 'EA = R1;');
-}};
diff --git a/arch/sparc/isa/formats/noop.isa b/arch/sparc/isa/formats/noop.isa
index fa4047f06..5007f5bcb 100644
--- a/arch/sparc/isa/formats/noop.isa
+++ b/arch/sparc/isa/formats/noop.isa
@@ -11,7 +11,7 @@ output header {{
         {
           protected:
             // Constructor
-            Noop(const char *mnem, MachInst _machInst, OpClass __opClass) :
+            Noop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
                 SparcStaticInst(mnem, _machInst, __opClass)
             {
             }
@@ -45,6 +45,6 @@ def format Noop(code, *opt_flags) {{
         iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        decode_block = BasicDecode.subst(iop)
         exec_output = NoopExecute.subst(iop)
 }};
diff --git a/arch/sparc/isa/formats/priv.isa b/arch/sparc/isa/formats/priv.isa
new file mode 100644
index 000000000..7c0d8a985
--- /dev/null
+++ b/arch/sparc/isa/formats/priv.isa
@@ -0,0 +1,172 @@
+////////////////////////////////////////////////////////////////////
+//
+// Privelege mode instructions
+//
+
+output header {{
+        /**
+         * Base class for privelege mode operations.
+         */
+        class Priv : public SparcStaticInst
+        {
+          protected:
+            // Constructor
+            Priv(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
+                SparcStaticInst(mnem, _machInst, __opClass)
+            {
+            }
+
+            std::string generateDisassembly(Addr pc,
+                    const SymbolTable *symtab) const;
+        };
+
+        /**
+         * Base class for user mode "tick" access.
+         */
+        class PrivTick : public SparcStaticInst
+        {
+          protected:
+            // Constructor
+            PrivTick(const char *mnem, ExtMachInst _machInst,
+                    OpClass __opClass) :
+                SparcStaticInst(mnem, _machInst, __opClass)
+            {
+            }
+
+            std::string generateDisassembly(Addr pc,
+                    const SymbolTable *symtab) const;
+        };
+
+        /**
+         * Base class for privelege mode operations with immediates.
+         */
+        class PrivImm : public Priv
+        {
+          protected:
+            // Constructor
+            PrivImm(const char *mnem, ExtMachInst _machInst,
+                    OpClass __opClass) :
+                Priv(mnem, _machInst, __opClass), imm(SIMM13)
+            {
+            }
+
+            uint32_t imm;
+        };
+
+        /**
+         * Base class for user mode "tick" access with immediates.
+         */
+        class PrivTickImm : public PrivTick
+        {
+          protected:
+            // Constructor
+            PrivTickImm(const char *mnem, ExtMachInst _machInst,
+                    OpClass __opClass) :
+                PrivTick(mnem, _machInst, __opClass), imm(SIMM13)
+            {
+            }
+
+            uint32_t imm;
+        };
+}};
+
+output decoder {{
+        std::string Priv::generateDisassembly(Addr pc,
+                const SymbolTable *symtab) const
+        {
+                return "Privileged Instruction";
+        }
+
+        std::string PrivTick::generateDisassembly(Addr pc,
+                const SymbolTable *symtab) const
+        {
+                return "Regular access to Tick";
+        }
+}};
+
+def template PrivExecute {{
+    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+            Trace::InstRecord *traceData) const
+    {
+        %(op_decl)s;
+        %(op_rd)s;
+
+        //If the processor isn't in privileged mode, fault out right away
+        if(!pstate_priv)
+            return new PrivilegedOpCode
+
+        %(code)s;
+        %(op_wb)s;
+    }
+}};
+
+def template PrivTickExecute {{
+    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+            Trace::InstRecord *traceData) const
+    {
+        %(op_decl)s;
+        %(op_rd)s;
+
+        //If the processor isn't in privileged mode, fault out right away
+        if(!pstate_priv && tick_npt)
+            return new PrivilegedAction
+
+        %(code)s;
+        %(op_wb)s;
+    }
+}};
+
+def template Rb2OrImm13Decode {{
+    {
+        return (I ? (SparcStaticInst *)(new %(class_name)sImm(machInst))
+                  : (SparcStaticInst *)(new %(class_name)s(machInst)));
+    }
+}};
+
+// Primary format for integer operate instructions:
+def format Priv(code, *opt_flags) {{
+        uses_imm = (code.find('Rs2_or_imm13') != -1)
+        if uses_imm:
+            orig_code = code
+            code = re.sub(r'Rs2_or_imm', 'Rs2', orig_code)
+            imm_code = re.sub(r'Rs2_or_imm(\.\w+)?', 'imm', orig_code)
+        cblk = CodeBlock(code)
+        iop = InstObjParams(name, Name, 'Priv', cblk, opt_flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        exec_output = PrivExecute.subst(iop)
+        if uses_imm:
+            imm_cblk = CodeBlock(imm_code)
+            imm_iop = InstObjParams(name, Name + 'Imm', 'PrivImm', imm_cblk,
+                                    opt_flags)
+            header_output += BasicDeclare.subst(imm_iop)
+            decoder_output += BasicConstructor.subst(imm_iop)
+            exec_output += PrivExecute.subst(imm_iop)
+            decode_block = Rb2OrImm13Decode.subst(iop)
+        else:
+            decode_block = BasicDecode.subst(iop)
+}};
+
+// Primary format for integer operate instructions:
+def format PrivTick(code, *opt_flags) {{
+        uses_imm = (code.find('Rs2_or_imm13') != -1)
+        if uses_imm:
+            orig_code = code
+            code = re.sub(r'Rs2_or_imm', 'Rs2', orig_code)
+            imm_code = re.sub(r'Rs2_or_imm(\.\w+)?', 'imm', orig_code)
+        cblk = CodeBlock(code)
+        iop = InstObjParams(name, Name, 'PrivTick', cblk, opt_flags)
+        header_output = BasicDeclare.subst(iop)
+        decoder_output = BasicConstructor.subst(iop)
+        exec_output = PrivTickExecute.subst(iop)
+        if uses_imm:
+            imm_cblk = CodeBlock(imm_code)
+            imm_iop = InstObjParams(name, Name + 'Imm', 'PrivTickImm', imm_cblk,
+                                    opt_flags)
+            header_output += BasicDeclare.subst(imm_iop)
+            decoder_output += BasicConstructor.subst(imm_iop)
+            exec_output += PrivTickExecute.subst(imm_iop)
+            decode_block = Rb2OrImm13Decode.subst(iop)
+        else:
+            decode_block = BasicDecode.subst(iop)
+}};
diff --git a/arch/sparc/isa/formats/trap.isa b/arch/sparc/isa/formats/trap.isa
index ff3aadf72..935fbfe6b 100644
--- a/arch/sparc/isa/formats/trap.isa
+++ b/arch/sparc/isa/formats/trap.isa
@@ -5,14 +5,15 @@
 
 output header {{
         /**
-         * Base class for integer operations.
+         * Base class for trap instructions,
+         * or instructions that always fault.
          */
         class Trap : public SparcStaticInst
         {
           protected:
 
             // Constructor
-            Trap(const char *mnem, MachInst _machInst, OpClass __opClass) :
+            Trap(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
                 SparcStaticInst(mnem, _machInst, __opClass)
             {
             }
@@ -34,18 +35,18 @@ def template TrapExecute {{
         Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                 Trace::InstRecord *traceData) const
         {
-            //TODO: set up a software fault and return it.
-            return NoFault;
+            Fault fault = NoFault;
+            %(code)s
+            return fault;
         }
 }};
 
-// Primary format for integer operate instructions:
 def format Trap(code, *opt_flags) {{
         orig_code = code
         cblk = CodeBlock(code)
         iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecodeWithMnemonic.subst(iop)
+        decode_block = BasicDecode.subst(iop)
         exec_output = TrapExecute.subst(iop)
 }};
diff --git a/arch/sparc/isa/formats/unknown.isa b/arch/sparc/isa/formats/unknown.isa
new file mode 100644
index 000000000..eeb2b9496
--- /dev/null
+++ b/arch/sparc/isa/formats/unknown.isa
@@ -0,0 +1,46 @@
+////////////////////////////////////////////////////////////////////
+//
+// Unknown instructions
+//
+
+output header {{
+        /**
+         * Class for Unknown/Illegal instructions
+         */
+        class Unknown : public SparcStaticInst
+        {
+          public:
+
+            // Constructor
+            Unknown(ExtMachInst _machInst) :
+                    SparcStaticInst("unknown", _machInst, No_OpClass)
+            {
+            }
+
+            %(BasicExecDeclare)s
+
+            std::string generateDisassembly(Addr pc,
+                    const SymbolTable *symtab) const;
+
+        };
+}};
+
+output decoder {{
+        std::string Unknown::generateDisassembly(Addr pc,
+                const SymbolTable *symtab) const
+        {
+            return "Unknown instruction\n";
+        }
+}};
+
+output exec {{
+        Fault Unknown::execute(%(CPU_exec_context)s *xc,
+                Trace::InstRecord *traceData) const
+        {
+            return new IllegalInstruction;
+        }
+}};
+
+def format Unknown() {{
+        decode_block = 'return new Unknown(machInst);\n'
+}};
diff --git a/arch/sparc/isa/includes.isa b/arch/sparc/isa/includes.isa
index 860f4657a..c39fc2ef9 100644
--- a/arch/sparc/isa/includes.isa
+++ b/arch/sparc/isa/includes.isa
@@ -39,5 +39,7 @@ output exec {{
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"
 #include "sim/sim_exit.hh"
+
+using namespace SparcISA;
 }};
 
diff --git a/arch/sparc/isa/operands.isa b/arch/sparc/isa/operands.isa
index 64f5abd08..abfdf7bcd 100644
--- a/arch/sparc/isa/operands.isa
+++ b/arch/sparc/isa/operands.isa
@@ -27,5 +27,84 @@ def operands {{
     #'Runiq': ('ControlReg', 'uq', 'Uniq', None, 1),
     #'FPCR':  ('ControlReg', 'uq', 'Fpcr', None, 1),
     'R0':  ('IntReg', 'udw', '0', None, 1),
-    'R16': ('IntReg', 'udw', '16', None, 1)
+    'R16': ('IntReg', 'udw', '16', None, 1),
+    # Control registers
+    'Pstate':		('ControlReg', 'udw', 'MISCREG_PSTATE', None, 1),
+    'PstateAg':		('ControlReg', 'udw', 'MISCREG_PSTATE_AG', None, 2),
+    'PstateIe':		('ControlReg', 'udw', 'MISCREG_PSTATE_IE', None, 3),
+    'PstatePriv':	('ControlReg', 'udw', 'MISCREG_PSTATE_PRIV', None, 4),
+    'PstateAm':		('ControlReg', 'udw', 'MISCREG_PSTATE_AM', None, 5),
+    'PstatePef':	('ControlReg', 'udw', 'MISCREG_PSTATE_PEF', None, 6),
+    'PstateRed':	('ControlReg', 'udw', 'MISCREG_PSTATE_RED', None, 7),
+    'PstateMm':		('ControlReg', 'udw', 'MISCREG_PSTATE_MM', None, 8),
+    'PstateTle':	('ControlReg', 'udw', 'MISCREG_PSTATE_TLE', None, 9),
+    'PstateCle':	('ControlReg', 'udw', 'MISCREG_PSTATE_CLE', None, 10),
+    'Tba':		('ControlReg', 'udw', 'MISCREG_TBA', None, 11),
+    'Y':		('ControlReg', 'udw', 'MISCREG_Y', None, 12),
+    'YValue':		('ControlReg', 'udw', 'MISCREG_Y_VALUE', None, 13),
+    'Pil':		('ControlReg', 'udw', 'MISCREG_PIL', None, 14),
+    'Cwp':		('ControlReg', 'udw', 'MISCREG_CWP', None, 15),
+    #'Tt':		('ControlReg', 'udw', 'MISCREG_TT_BASE + tl', None, 16),
+    'Ccr':		('ControlReg', 'udw', 'MISCREG_CCR', None, 17),
+    'CcrIcc':		('ControlReg', 'udw', 'MISCREG_CCR_ICC', None, 18),
+    'CcrIccC':		('ControlReg', 'udw', 'MISCREG_CCR_ICC_C', None, 19),
+    'CcrIccV':		('ControlReg', 'udw', 'MISCREG_CCR_ICC_V', None, 20),
+    'CcrIccZ':		('ControlReg', 'udw', 'MISCREG_CCR_ICC_Z', None, 21),
+    'CcrIccN':		('ControlReg', 'udw', 'MISCREG_CCR_ICC_N', None, 22),
+    'CcrXcc':		('ControlReg', 'udw', 'MISCREG_CCR_XCC', None, 23),
+    'CcrXccC':		('ControlReg', 'udw', 'MISCREG_CCR_XCC_C', None, 22),
+    'CcrXccV':		('ControlReg', 'udw', 'MISCREG_CCR_XCC_V', None, 23),
+    'CcrXccZ':		('ControlReg', 'udw', 'MISCREG_CCR_XCC_Z', None, 24),
+    'CcrXccN':		('ControlReg', 'udw', 'MISCREG_XCC_N', None, 25),
+    'Asi':		('ControlReg', 'udw', 'MISCREG_ASI', None, 26),
+    'Tl':		('ControlReg', 'udw', 'MISCREG_TL', None, 27),
+    #'Tpc':		('ControlReg', 'udw', 'MISCREG_TPC', None, 28),
+    'Tick':		('ControlReg', 'udw', 'MISCREG_TICK', None, 29),
+    'TickCounter':	('ControlReg', 'udw', 'MISCREG_TICK_COUNTER', None, 32),
+    'TickNpt':		('ControlReg', 'udw', 'MISCREG_TICK_NPT', None, 33),
+    'Cansave':		('ControlReg', 'udw', 'MISCREG_CANSAVE', None, 34),
+    'Canrestore':	('ControlReg', 'udw', 'MISCREG_CANRESTORE', None, 35),
+    'Otherwin':		('ControlReg', 'udw', 'MISCREG_OTHERWIN', None, 36),
+    'Cleanwin':		('ControlReg', 'udw', 'MISCREG_CLEANWIN', None, 37),
+    'Wstate':		('ControlReg', 'udw', 'MISCREG_WSTATE', None, 38),
+    'WstateNormal':	('ControlReg', 'udw', 'MISCREG_WSTATE_NORMAL', None,39),
+    'WstateOther':	('ControlReg', 'udw', 'MISCREG_WSTATE_OTHER', None, 40),
+    'Ver':		('ControlReg', 'udw', 'MISCREG_VER', None, 41),
+    'VerMaxwin':	('ControlReg', 'udw', 'MISCREG_VER_MAXWIN', None, 42),
+    'VerMaxtl':		('ControlReg', 'udw', 'MISCREG_VER_MAXTL', None, 43),
+    'VerMask':		('ControlReg', 'udw', 'MISCREG_VER_MASK', None, 44),
+    'VerImpl':		('ControlReg', 'udw', 'MISCREG_VER_MASK', None, 45),
+    'VerManuf':		('ControlReg', 'udw', 'MISCREG_VER_MANUF', None, 46),
+    'Fsr':		('ControlReg', 'udw', 'MISCREG_FSR', None, 47),
+    'FsrCexc':		('ControlReg', 'udw', 'MISCREG_FSR_CEXC', None, 48),
+    'FsrCexcNxc':	('ControlReg', 'udw', 'MISCREG_FSR_CEXC_NXC', None, 49),
+    'FsrCexcDzc':	('ControlReg', 'udw', 'MISCREG_FSR_CEXC_DZC', None, 50),
+    'FsrCexcUfc':	('ControlReg', 'udw', 'MISCREG_FSR_CEXC_UFC', None, 51),
+    'FsrCexcOfc':	('ControlReg', 'udw', 'MISCREG_FSR_CEXC_OFC', None, 52),
+    'FsrCexcNvc':	('ControlReg', 'udw', 'MISCREG_FSR_CEXC_NVC', None, 53),
+    'FsrAexc':		('ControlReg', 'udw', 'MISCREG_FSR_AEXC', None, 54),
+    'FsrAexcNxc':	('ControlReg', 'udw', 'MISCREG_FSR_AEXC_NXC', None, 55),
+    'FsrAexcDzc':	('ControlReg', 'udw', 'MISCREG_FSR_AEXC_DZC', None, 56),
+    'FsrAexcUfc':	('ControlReg', 'udw', 'MISCREG_FSR_AEXC_UFC', None, 57),
+    'FsrAexcOfc':	('ControlReg', 'udw', 'MISCREG_FSR_AEXC_OFC', None, 58),
+    'FsrAexcNvc':	('ControlReg', 'udw', 'MISCREC_FSR_AEXC_NVC', None, 59),
+    'FsrFcc0':		('ControlReg', 'udw', 'MISCREG_FSR_FCC0', None, 60),
+    'FsrQne':		('ControlReg', 'udw', 'MISCREG_FSR_QNE', None, 61),
+    'FsrFtt':		('ControlReg', 'udw', 'MISCREG_FSR_FTT', None, 62),
+    'FsrVer':		('ControlReg', 'udw', 'MISCREG_FSR_VER', None, 63),
+    'FsrNs':		('ControlReg', 'udw', 'MISCREG_FSR_NS', None, 64),
+    'FsrTem':		('ControlReg', 'udw', 'MISCREG_FSR_TEM', None, 65),
+    'FsrTemNxm':	('ControlReg', 'udw', 'MISCREG_FSR_TEM_NXM', None, 66),
+    'FsrTemDzm':	('ControlReg', 'udw', 'MISCREG_FSR_TEM_DZM', None, 67),
+    'FsrTemUfm':	('ControlReg', 'udw', 'MISCREG_FSR_TEM_UFM', None, 68),
+    'FsrTemOfm':	('ControlReg', 'udw', 'MISCREG_FSR_TEM_OFM', None, 69),
+    'FsrTemNvm':	('ControlReg', 'udw', 'MISCREG_FSR_TEM_NVM', None, 70),
+    'FsrRd':		('ControlReg', 'udw', 'MISCREG_FSR_RD', None, 71),
+    'FsrFcc1':		('ControlReg', 'udw', 'MISCREG_FSR_FCC1', None, 72),
+    'FsrFcc2':		('ControlReg', 'udw', 'MISCREG_FSR_FCC2', None, 73),
+    'FsrFcc3':		('ControlReg', 'udw', 'MISCREG_FSR_FCC3', None, 74),
+    'Fprs':		('ControlReg', 'udw', 'MISCREG_FPRS', None, 75),
+    'FprsDl':		('ControlReg', 'udw', 'MISCREG_FPRS_DL', None, 76),
+    'FprsDu':		('ControlReg', 'udw', 'MISCREG_FPRS_DU', None, 77),
+    'FprsFef':		('ControlReg', 'udw', 'MISCREG_FPRS_FEF', None, 78)
 }};
diff --git a/arch/sparc/isa_traits.hh b/arch/sparc/isa_traits.hh
index ad8ae5c8d..0955abb3a 100644
--- a/arch/sparc/isa_traits.hh
+++ b/arch/sparc/isa_traits.hh
@@ -83,6 +83,15 @@ class SyscallReturn
 
 namespace SparcISA
 {
+
+    // These enumerate all the registers for dependence tracking.
+    enum DependenceTags {
+        // 0..31 are the integer regs 0..31
+        // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
+        FP_Base_DepTag = 32,
+        Ctrl_Base_DepTag = 96,
+    };
+
     //This makes sure the big endian versions of certain functions are used.
     using namespace BigEndianGuest;
 
@@ -142,7 +151,7 @@ namespace SparcISA
 
     void unserialize(Checkpoint *cp, const std::string &section);
 
-    StaticInstPtr decodeInst(MachInst);
+    StaticInstPtr decodeInst(ExtMachInst);
 
     // return a no-op instruction... used for instruction fetch faults
     extern const MachInst NoopMachInst;