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| author | Ali Saidi <saidi@eecs.umich.edu> | 2006-03-15 18:12:01 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2006-03-15 18:12:01 -0500 |
| commit | 7359e2df01fde9ea34a0ba661750a455e26bcacd (patch) | |
| tree | f584d8fce74b08639346b80003f735d53f0e94e0 /arch/sparc | |
| parent | 97e424982ad99348bc27ab2ca79d0861cddfe4d1 (diff) | |
| download | gem5-7359e2df01fde9ea34a0ba661750a455e26bcacd.tar.xz | |
implement the Tcc instruction to call syscall.
arch/sparc/isa/bitfields.isa:
the trap field is 7:0
arch/sparc/isa/decoder.isa:
add code to in the Tcc instruction to call a syscall
arch/sparc/isa_traits.hh:
We need the syscall num register
--HG--
extra : convert_revision : 0861ec1dd8c7cac57765b22bc408fdffbe63fe2a
Diffstat (limited to 'arch/sparc')
| -rw-r--r-- | arch/sparc/isa/bitfields.isa | 2 | ||||
| -rw-r--r-- | arch/sparc/isa/decoder.isa | 18 | ||||
| -rw-r--r-- | arch/sparc/isa_traits.hh | 1 |
3 files changed, 18 insertions, 3 deletions
diff --git a/arch/sparc/isa/bitfields.isa b/arch/sparc/isa/bitfields.isa index b0ac57575..237f0fa64 100644 --- a/arch/sparc/isa/bitfields.isa +++ b/arch/sparc/isa/bitfields.isa @@ -46,5 +46,5 @@ def bitfield SHCNT64 <5:0>; def bitfield SIMM10 <9:0>; def bitfield SIMM11 <10:0>; def bitfield SIMM13 <12:0>; -def bitfield SW_TRAP <6:0>; +def bitfield SW_TRAP <7:0>; def bitfield X <12>; diff --git a/arch/sparc/isa/decoder.isa b/arch/sparc/isa/decoder.isa index eaf3aab3b..716653d84 100644 --- a/arch/sparc/isa/decoder.isa +++ b/arch/sparc/isa/decoder.isa @@ -532,12 +532,26 @@ decode OP default Trap::unknown({{IllegalInstruction}}) { case 1: case 3: throw illegal_instruction; case 0: +#if FULL_SYSTEM + throw trap_instruction; +#else if(passesCondition(xc->regs.MiscRegs.ccrFields.icc, machInst<25:28>)) - throw trap_instruction; + // At least glibc only uses trap 0, + // solaris/sunos may use others + assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0); + xc->syscall(); +#endif break; case 2: +#if FULL_SYSTEM + throw trap_instruction; +#else if(passesCondition(xc->regs.MiscRegs.ccrFields.xcc, machInst<25:28>)) - throw trap_instruction; + // At least glibc only uses trap 0, + // solaris/sunos may use others + assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0); + xc->syscall(); +#endif break; } }}); //Tcc diff --git a/arch/sparc/isa_traits.hh b/arch/sparc/isa_traits.hh index 23e3dad74..ad8ae5c8d 100644 --- a/arch/sparc/isa_traits.hh +++ b/arch/sparc/isa_traits.hh @@ -106,6 +106,7 @@ namespace SparcISA const int ArgumentReg3 = 11; const int ArgumentReg4 = 12; const int ArgumentReg5 = 13; + const int SyscallNumReg = 1; // Some OS syscall sue a second register (o1) to return a second value const int SyscallPseudoReturnReg = ArgumentReg1; |