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| author | Kevin Lim <ktlim@umich.edu> | 2005-03-10 15:53:27 -0500 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2005-03-10 15:53:27 -0500 |
| commit | c12a665c3120b61ed4e09da5d8a52c57406763d5 (patch) | |
| tree | b5176be0d526ea24cafcd6f615058651f2b34dfb /arch | |
| parent | aa8c9db159422a313f6dfc9a76fd827515b32126 (diff) | |
| parent | 51108a8c0a3a42702f49a945f8a4dac776a8d189 (diff) | |
| download | gem5-c12a665c3120b61ed4e09da5d8a52c57406763d5.tar.xz | |
Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5
--HG--
extra : convert_revision : a58535776cf5a3d17f8d9f65144cdf8db54289aa
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/alpha/isa_desc | 12 | ||||
| -rw-r--r-- | arch/alpha/isa_traits.hh | 4 | ||||
| -rwxr-xr-x | arch/isa_parser.py | 6 |
3 files changed, 16 insertions, 6 deletions
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index 0e07400d3..904af3ef0 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -744,9 +744,9 @@ output header {{ /// Memory request flags. See mem_req_base.hh. unsigned memAccessFlags; /// Pointer to EAComp object. - const StaticInstPtr<AlphaISA> eaCompPtr; + StaticInstPtr<AlphaISA> eaCompPtr; /// Pointer to MemAcc object. - const StaticInstPtr<AlphaISA> memAccPtr; + StaticInstPtr<AlphaISA> memAccPtr; /// Constructor Memory(const char *mnem, MachInst _machInst, OpClass __opClass, @@ -762,8 +762,8 @@ output header {{ public: - const StaticInstPtr<AlphaISA> &eaCompInst() const { return eaCompPtr; } - const StaticInstPtr<AlphaISA> &memAccInst() const { return memAccPtr; } + StaticInstPtr<AlphaISA> &eaCompInst() { return eaCompPtr; } + StaticInstPtr<AlphaISA> &memAccInst() { return memAccPtr; } }; /** @@ -2539,9 +2539,9 @@ decode OPCODE default Unknown::unknown() { xc->syscall(); }}, IsNonSpeculative); // Read uniq reg into ABI return value register (r0) - 0x9e: rduniq({{ R0 = Runiq; }}); + 0x9e: rduniq({{ R0 = Runiq; }}, IsNonSpeculative); // Write uniq reg with value from ABI arg register (r16) - 0x9f: wruniq({{ Runiq = R16; }}); + 0x9f: wruniq({{ Runiq = R16; }}, IsNonSpeculative); } } #endif diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh index 9327fa88b..9c7709a60 100644 --- a/arch/alpha/isa_traits.hh +++ b/arch/alpha/isa_traits.hh @@ -148,6 +148,10 @@ static const Addr PageOffset = PageBytes - 1; NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs }; + enum { + TotalDataRegs = NumIntRegs + NumFloatRegs + }; + typedef union { IntReg intreg; FloatReg fpreg; diff --git a/arch/isa_parser.py b/arch/isa_parser.py index 18e4b0a45..5e0267c9e 100755 --- a/arch/isa_parser.py +++ b/arch/isa_parser.py @@ -639,6 +639,12 @@ CpuModel('FastCPU', 'fast_cpu_exec.cc', CpuModel('FullCPU', 'full_cpu_exec.cc', '#include "cpu/full_cpu/dyn_inst.hh"', { 'CPU_exec_context': 'DynInst' }) +CpuModel('AlphaFullCPU', 'alpha_full_cpu_exec.cc', + '#include "cpu/beta_cpu/alpha_dyn_inst.hh"', + { 'CPU_exec_context': 'AlphaDynInst<AlphaSimpleImpl>' }) +CpuModel('OoOCPU', 'ooo_cpu_exec.cc', + '#include "cpu/ooo_cpu/ooo_dyn_inst.hh"', + { 'CPU_exec_context': 'OoODynInst<OoOImpl>' }) # Expand template with CPU-specific references into a dictionary with # an entry for each CPU model name. The entry key is the model name |