Fixes for detailed boot, made cttz and ctlz instructions more compact,

and started cleaning up config files.

arch/alpha/isa_desc:
    Made implementation of cttz and ctlz more compact
base/remote_gdb.cc:
    Added comment about PALcode debugger accesses
dev/baddev.cc:
dev/baddev.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunami_uart.cc:
dev/tsunami_uart.hh:
    Cleaned up includes and changed device from FunctionalMemory to
    PioDevice for detailed boot
dev/ns_gige.cc:
    The ethernet dev uses two BARs, and the first bars size was being set
    incorrectly.
dev/tsunamireg.h:
    I don't know why we were using the superpage as the PCI memory addr.
    Changed and works correctly with detailed boot.

--HG--
extra : convert_revision : b535e76612cb90b544305dc1aa8c5e0e774564bd

1 files changed, 23 insertions, 58 deletions

diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index 06a1081bc..080699ddb 100644
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -2119,65 +2119,30 @@ decode OPCODE default Unknown::unknown() {
 	0x1c: decode INTFUNC {
 	    0x00: decode RA { 31: sextb({{ Rc.sb = Rb_or_imm< 7:0>; }}); }
 	    0x01: decode RA { 31: sextw({{ Rc.sw = Rb_or_imm<15:0>; }}); }
-		0x32: ctlz({{
-        uint64_t count = 0;
-        uint64_t temp = Rb;
-        if (temp & ULL(0xffffffff00000000))
-           temp >>= 32;
-         else 
-            count += 32;
-        if (temp & ULL(0xffff0000)) 
-           temp >>= 16;
-        else 
-            count += 16;
-        if (temp & ULL(0xff00)) 
-           temp >>= 8;
-        else 
-            count += 8;
-        if (temp & ULL(0xf0)) 
-           temp >>= 4;
-        else 
-            count += 4;
-        if (temp & ULL(0xC)) 
-           temp >>= 2;
-        else 
-            count += 2;
-        if (temp & ULL(0x2)) 
-           temp >>= 1;
-        else 
-            count += 1;
-        if ((temp & ULL(0x1)) != 0x1)
-            count += 1;
-        Rc = count; 
-              }}, IntAluOp);
+        0x32: ctlz({{
+            uint64_t count = 0;
+            uint64_t temp = Rb;
+            if (temp<63:32>) temp >>= 32; else count += 32;
+            if (temp<31:16>) temp >>= 16; else count += 16;
+            if (temp<15:8>) temp >>= 8; else count += 8;
+            if (temp<7:4>) temp >>= 4; else count += 4;
+            if (temp<3:2>) temp >>= 2; else count += 2;
+            if (temp<1:1>) temp >>= 1; else count += 1;
+            if ((temp<0:0>) != 0x1) count += 1; 
+            Rc = count; 
+            }}, IntAluOp);
          
-		0x33: cttz({{
-        uint64_t count = 0;
-        uint64_t temp = Rb;
-        if (!(temp & ULL(0x00000000ffffffff))) {
-            temp >>= 32;
-            count += 32;
-        }
-        if (!(temp & ULL(0x0000ffff))) {
-            temp >>= 16;
-            count += 16;
-        }
-        if (!(temp & ULL(0x00ff))) {
-            temp >>= 8;
-            count += 8;
-        }
-        if (!(temp & ULL(0x0f))) {
-            temp >>= 4;
-            count += 4;
-        }
-        if (!(temp & ULL(0x3))) {
-            temp >>= 2;
-            count += 2;
-        }
-        if (!(temp & ULL(0x1)))
-            count += 1;
-        Rc = count;
-              }}, IntAluOp);
+        0x33: cttz({{
+            uint64_t count = 0;
+            uint64_t temp = Rb;
+            if (!(temp<31:0>)) { temp >>= 32; count += 32; }
+            if (!(temp<15:0>)) { temp >>= 16; count += 16; }
+            if (!(temp<7:0>)) { temp >>= 8; count += 8; }
+            if (!(temp<3:0>)) { temp >>= 4; count += 4; }
+            if (!(temp<1:0>)) { temp >>= 2; count += 2; }
+            if (!(temp<0:0> & ULL(0x1))) count += 1; 
+            Rc = count; 
+        }}, IntAluOp);
 
 	    format FailUnimpl {
 		0x30: ctpop();