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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2004-04-03 13:46:10 -0800 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2004-04-03 13:46:10 -0800 |
| commit | 65205b82acee56b0034c0122d5f5a89f57c760fc (patch) | |
| tree | 6492d870fa53ee592ca81cafef74e930254351b3 /arch | |
| parent | b3b0a4705b27a192226e6f97dc78b97eec73613d (diff) | |
| download | gem5-65205b82acee56b0034c0122d5f5a89f57c760fc.tar.xz | |
More {Itb,Dtb} -> {ITB,DTB} renames (forgot to test build KERNEL).
Also missed renames in a bunch of config files somehow.
(See previous changeset for list of renames.)
arch/alpha/alpha_memory.cc:
arch/alpha/ev5.cc:
arch/alpha/faults.hh:
cpu/exec_context.cc:
cpu/exec_context.hh:
cpu/simple_cpu/simple_cpu.hh:
More {Itb,Dtb} -> {ITB,DTB} renames (forgot to test build KERNEL).
--HG--
extra : convert_revision : b2c6ca0916b72b59895520fcacaf028667560a0d
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/alpha/alpha_memory.cc | 12 | ||||
| -rw-r--r-- | arch/alpha/ev5.cc | 10 | ||||
| -rw-r--r-- | arch/alpha/faults.hh | 10 |
3 files changed, 16 insertions, 16 deletions
diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc index 13cdb1d73..dea25a440 100644 --- a/arch/alpha/alpha_memory.cc +++ b/arch/alpha/alpha_memory.cc @@ -465,7 +465,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const req->xc); if (write) { write_acv++; } else { read_acv++; } - return Dtb_Fault_Fault; + return DTB_Fault_Fault; } // Check for "superpage" mapping: when SP<1> is set, and @@ -480,7 +480,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const ((write ? MM_STAT_WR_MASK : 0) | MM_STAT_ACV_MASK), req->xc); if (write) { write_acv++; } else { read_acv++; } - return Dtb_Acv_Fault; + return DTB_Acv_Fault; } req->paddr = req->vaddr & PA_IMPL_MASK; @@ -512,13 +512,13 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const (pte->fonw ? MM_STAT_FONW_MASK : 0), req->xc); write_acv++; - return Dtb_Fault_Fault; + return DTB_Fault_Fault; } if (pte->fonw) { fault(req->vaddr, MM_STAT_WR_MASK | MM_STAT_FONW_MASK, req->xc); write_acv++; - return Dtb_Fault_Fault; + return DTB_Fault_Fault; } } else { if (!(pte->xre & MODE2MASK(mode))) { @@ -527,12 +527,12 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const (pte->fonr ? MM_STAT_FONR_MASK : 0), req->xc); read_acv++; - return Dtb_Acv_Fault; + return DTB_Acv_Fault; } if (pte->fonr) { fault(req->vaddr, MM_STAT_FONR_MASK, req->xc); read_acv++; - return Dtb_Fault_Fault; + return DTB_Fault_Fault; } } } diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index 551cbdabf..9b3ac5fff 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -68,11 +68,11 @@ AlphaISA::fault_addr[Num_Faults] = { 0x0201, /* Ndtb_Miss_Fault */ 0x0281, /* Pdtb_Miss_Fault */ 0x0301, /* Alignment_Fault */ - 0x0381, /* Dtb_Fault_Fault */ - 0x0381, /* Dtb_Acv_Fault */ - 0x0181, /* Itb_Miss_Fault */ - 0x0181, /* Itb_Fault_Fault */ - 0x0081, /* Itb_Acv_Fault */ + 0x0381, /* DTB_Fault_Fault */ + 0x0381, /* DTB_Acv_Fault */ + 0x0181, /* ITB_Miss_Fault */ + 0x0181, /* ITB_Fault_Fault */ + 0x0081, /* ITB_Acv_Fault */ 0x0481, /* Unimplemented_Opcode_Fault */ 0x0581, /* Fen_Fault */ 0x2001, /* Pal_Fault */ diff --git a/arch/alpha/faults.hh b/arch/alpha/faults.hh index bc8a4da0e..33aa55439 100644 --- a/arch/alpha/faults.hh +++ b/arch/alpha/faults.hh @@ -38,11 +38,11 @@ enum Fault { Ndtb_Miss_Fault, // DTB miss Pdtb_Miss_Fault, // nested DTB miss Alignment_Fault, // unaligned access - Dtb_Fault_Fault, // DTB page fault - Dtb_Acv_Fault, // DTB access violation - Itb_Miss_Fault, // ITB miss - Itb_Fault_Fault, // ITB page fault - Itb_Acv_Fault, // ITB access violation + DTB_Fault_Fault, // DTB page fault + DTB_Acv_Fault, // DTB access violation + ITB_Miss_Fault, // ITB miss + ITB_Fault_Fault, // ITB page fault + ITB_Acv_Fault, // ITB access violation Unimplemented_Opcode_Fault, // invalid/unimplemented instruction Fen_Fault, // FP not-enabled fault Pal_Fault, // call_pal S/W interrupt |