Pseudo instructions are now passed whatever instructions they need by the decoder, rather than extracting them explicitly. This lets most of the pseudo instruction code to be shared across architectures.

SConscript:
    Moved pseudo_inst.hh from targetarch to full system sources
arch/alpha/SConscript:
    Moved pseudo_inst.cc out of the alpha specific sources
arch/alpha/isa/decoder.isa:
    The decoder now pulls out the arguments for the pseudo instructions based on the alpha ABI
arch/alpha/isa/main.isa:
    Registers 16, 17 and 18 are used to get parameters for the pseudo instructions and can be referred to explicitly
sim/pseudo_inst.cc:
    Changed some include paths to reflect that pseudo_inst.hh is now outside of the alpha directory. Also, instead of extracting their parameters directly, they're passed in as regular function arguments.
sim/pseudo_inst.hh:
    Changed the function prototypes to include the functions parameters, now that they aren't extracted from the execution context.

--HG--
rename : arch/alpha/pseudo_inst.cc => sim/pseudo_inst.cc
rename : arch/alpha/pseudo_inst.hh => sim/pseudo_inst.hh
extra : convert_revision : 76ce768cf1d8a838aa7b64878a7ab4c4215ac999

5 files changed, 10 insertions, 319 deletions

diff --git a/arch/alpha/SConscript b/arch/alpha/SConscript
index 2c98125bc..8bf408c06 100644
--- a/arch/alpha/SConscript
+++ b/arch/alpha/SConscript
@@ -244,7 +244,6 @@ arch_full_system_sources = Split('''
 	arch/alpha/arguments.cc
 	arch/alpha/ev5.cc
 	arch/alpha/osfpal.cc
-	arch/alpha/pseudo_inst.cc
 	arch/alpha/stacktrace.cc
 	arch/alpha/vtophys.cc
 	''')
diff --git a/arch/alpha/isa/decoder.isa b/arch/alpha/isa/decoder.isa
index 29124f191..aff8571e9 100644
--- a/arch/alpha/isa/decoder.isa
+++ b/arch/alpha/isa/decoder.isa
@@ -768,23 +768,23 @@ decode OPCODE default Unknown::unknown() {
                 AlphaPseudo::m5exit_old(xc->xcBase());
             }}, No_OpClass, IsNonSpeculative);
             0x21: m5exit({{
-                AlphaPseudo::m5exit(xc->xcBase());
+                AlphaPseudo::m5exit(xc->xcBase(), R16);
             }}, No_OpClass, IsNonSpeculative);
             0x30: initparam({{ Ra = xc->xcBase()->cpu->system->init_param; }});
             0x40: resetstats({{
-                AlphaPseudo::resetstats(xc->xcBase());
+                AlphaPseudo::resetstats(xc->xcBase(), R16, R17);
             }}, IsNonSpeculative);
             0x41: dumpstats({{
-                AlphaPseudo::dumpstats(xc->xcBase());
+                AlphaPseudo::dumpstats(xc->xcBase(), R16, R17);
             }}, IsNonSpeculative);
             0x42: dumpresetstats({{
-                AlphaPseudo::dumpresetstats(xc->xcBase());
+                AlphaPseudo::dumpresetstats(xc->xcBase(), R16, R17);
             }}, IsNonSpeculative);
             0x43: m5checkpoint({{
-                AlphaPseudo::m5checkpoint(xc->xcBase());
+                AlphaPseudo::m5checkpoint(xc->xcBase(), R16, R17);
             }}, IsNonSpeculative);
             0x50: m5readfile({{
-                AlphaPseudo::readfile(xc->xcBase());
+                R0 = AlphaPseudo::readfile(xc->xcBase(), R16, R17, R18);
             }}, IsNonSpeculative);
             0x51: m5break({{
                 AlphaPseudo::debugbreak(xc->xcBase());
@@ -793,7 +793,7 @@ decode OPCODE default Unknown::unknown() {
                 AlphaPseudo::switchcpu(xc->xcBase());
             }}, IsNonSpeculative);
             0x53: m5addsymbol({{
-                AlphaPseudo::addsymbol(xc->xcBase());
+                AlphaPseudo::addsymbol(xc->xcBase(), R16, R17);
             }}, IsNonSpeculative);
 
         }
diff --git a/arch/alpha/isa/main.isa b/arch/alpha/isa/main.isa
index c082df8c8..a2860f17b 100644
--- a/arch/alpha/isa/main.isa
+++ b/arch/alpha/isa/main.isa
@@ -160,7 +160,9 @@ def operands {{
     'FPCR':  (' ControlReg', 'uq', 'Fpcr', None, 1),
     # The next two are hacks for non-full-system call-pal emulation
     'R0':  ('IntReg', 'uq', '0', None, 1),
-    'R16': ('IntReg', 'uq', '16', None, 1)
+    'R16': ('IntReg', 'uq', '16', None, 1),
+    'R17': ('IntReg', 'uq', '17', None, 1),
+    'R18': ('IntReg', 'uq', '18', None, 1)
 }};
 
 ////////////////////////////////////////////////////////////////////
diff --git a/arch/alpha/pseudo_inst.cc b/arch/alpha/pseudo_inst.cc
deleted file mode 100644
index d6f622ba2..000000000
--- a/arch/alpha/pseudo_inst.cc
+++ /dev/null
@@ -1,256 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <errno.h>
-#include <fcntl.h>
-#include <unistd.h>
-#include <cstdio>
-
-#include <string>
-
-#include "arch/alpha/pseudo_inst.hh"
-#include "arch/alpha/vtophys.hh"
-#include "cpu/base.hh"
-#include "cpu/sampler/sampler.hh"
-#include "cpu/exec_context.hh"
-#include "kern/kernel_stats.hh"
-#include "sim/param.hh"
-#include "sim/serialize.hh"
-#include "sim/sim_exit.hh"
-#include "sim/stat_control.hh"
-#include "sim/stats.hh"
-#include "sim/system.hh"
-#include "sim/debug.hh"
-#include "sim/vptr.hh"
-
-using namespace std;
-
-extern Sampler *SampCPU;
-
-using namespace Stats;
-
-namespace AlphaPseudo
-{
-    bool doStatisticsInsts;
-    bool doCheckpointInsts;
-    bool doQuiesce;
-
-    void
-    arm(ExecContext *xc)
-    {
-        xc->kernelStats->arm();
-    }
-
-    void
-    quiesce(ExecContext *xc)
-    {
-        if (!doQuiesce)
-            return;
-
-        xc->suspend();
-        xc->kernelStats->quiesce();
-    }
-
-    void
-    ivlb(ExecContext *xc)
-    {
-        xc->kernelStats->ivlb();
-    }
-
-    void
-    ivle(ExecContext *xc)
-    {
-    }
-
-    void
-    m5exit_old(ExecContext *xc)
-    {
-        SimExit(curTick, "m5_exit_old instruction encountered");
-    }
-
-    void
-    m5exit(ExecContext *xc)
-    {
-        Tick delay = xc->regs.intRegFile[16];
-        Tick when = curTick + delay * Clock::Int::ns;
-        SimExit(when, "m5_exit instruction encountered");
-    }
-
-    void
-    resetstats(ExecContext *xc)
-    {
-        if (!doStatisticsInsts)
-            return;
-
-        Tick delay = xc->regs.intRegFile[16];
-        Tick period = xc->regs.intRegFile[17];
-
-        Tick when = curTick + delay * Clock::Int::ns;
-        Tick repeat = period * Clock::Int::ns;
-
-        using namespace Stats;
-        SetupEvent(Reset, when, repeat);
-    }
-
-    void
-    dumpstats(ExecContext *xc)
-    {
-        if (!doStatisticsInsts)
-            return;
-
-        Tick delay = xc->regs.intRegFile[16];
-        Tick period = xc->regs.intRegFile[17];
-
-        Tick when = curTick + delay * Clock::Int::ns;
-        Tick repeat = period * Clock::Int::ns;
-
-        using namespace Stats;
-        SetupEvent(Dump, when, repeat);
-    }
-
-    void
-    addsymbol(ExecContext *xc)
-    {
-        Addr addr = xc->regs.intRegFile[16];
-        char symb[100];
-        CopyString(xc, symb, xc->regs.intRegFile[17], 100);
-        std::string symbol(symb);
-
-        DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr);
-
-        xc->system->kernelSymtab->insert(addr,symbol);
-    }
-
-    void
-    dumpresetstats(ExecContext *xc)
-    {
-        if (!doStatisticsInsts)
-            return;
-
-        Tick delay = xc->regs.intRegFile[16];
-        Tick period = xc->regs.intRegFile[17];
-
-        Tick when = curTick + delay * Clock::Int::ns;
-        Tick repeat = period * Clock::Int::ns;
-
-        using namespace Stats;
-        SetupEvent(Dump|Reset, when, repeat);
-    }
-
-    void
-    m5checkpoint(ExecContext *xc)
-    {
-        if (!doCheckpointInsts)
-            return;
-
-        Tick delay = xc->regs.intRegFile[16];
-        Tick period = xc->regs.intRegFile[17];
-
-        Tick when = curTick + delay * Clock::Int::ns;
-        Tick repeat = period * Clock::Int::ns;
-
-        Checkpoint::setup(when, repeat);
-    }
-
-    void
-    readfile(ExecContext *xc)
-    {
-        const string &file = xc->cpu->system->params->readfile;
-        if (file.empty()) {
-            xc->regs.intRegFile[0] = ULL(0);
-            return;
-        }
-
-        Addr vaddr = xc->regs.intRegFile[16];
-        uint64_t len = xc->regs.intRegFile[17];
-        uint64_t offset = xc->regs.intRegFile[18];
-        uint64_t result = 0;
-
-        int fd = ::open(file.c_str(), O_RDONLY, 0);
-        if (fd < 0)
-            panic("could not open file %s\n", file);
-
-        if (::lseek(fd, offset, SEEK_SET) < 0)
-            panic("could not seek: %s", strerror(errno));
-
-        char *buf = new char[len];
-        char *p = buf;
-        while (len > 0) {
-            int bytes = ::read(fd, p, len);
-            if (bytes <= 0)
-                break;
-
-            p += bytes;
-            result += bytes;
-            len -= bytes;
-        }
-
-        close(fd);
-        CopyIn(xc, vaddr, buf, result);
-        delete [] buf;
-        xc->regs.intRegFile[0] = result;
-    }
-
-    class Context : public ParamContext
-    {
-      public:
-        Context(const string &section) : ParamContext(section) {}
-        void checkParams();
-    };
-
-    Context context("pseudo_inst");
-
-    Param<bool> __quiesce(&context, "quiesce",
-                          "enable quiesce instructions",
-                          true);
-    Param<bool> __statistics(&context, "statistics",
-                             "enable statistics pseudo instructions",
-                             true);
-    Param<bool> __checkpoint(&context, "checkpoint",
-                             "enable checkpoint pseudo instructions",
-                             true);
-
-    void
-    Context::checkParams()
-    {
-        doQuiesce = __quiesce;
-        doStatisticsInsts = __statistics;
-        doCheckpointInsts = __checkpoint;
-    }
-
-    void debugbreak(ExecContext *xc)
-    {
-        debug_break();
-    }
-
-    void switchcpu(ExecContext *xc)
-    {
-        if (SampCPU)
-            SampCPU->switchCPUs();
-    }
-}
diff --git a/arch/alpha/pseudo_inst.hh b/arch/alpha/pseudo_inst.hh
deleted file mode 100644
index 0e7462a56..000000000
--- a/arch/alpha/pseudo_inst.hh
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (c) 2003-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-class ExecContext;
-
-namespace AlphaPseudo
-{
-    /**
-     * @todo these externs are only here for a hack in fullCPU::takeOver...
-     */
-    extern bool doStatisticsInsts;
-    extern bool doCheckpointInsts;
-    extern bool doQuiesce;
-
-    void arm(ExecContext *xc);
-    void quiesce(ExecContext *xc);
-    void ivlb(ExecContext *xc);
-    void ivle(ExecContext *xc);
-    void m5exit(ExecContext *xc);
-    void m5exit_old(ExecContext *xc);
-    void resetstats(ExecContext *xc);
-    void dumpstats(ExecContext *xc);
-    void dumpresetstats(ExecContext *xc);
-    void m5checkpoint(ExecContext *xc);
-    void readfile(ExecContext *xc);
-    void debugbreak(ExecContext *xc);
-    void switchcpu(ExecContext *xc);
-    void addsymbol(ExecContext *xc);
-}