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| author | Kevin Lim <ktlim@umich.edu> | 2005-01-11 19:00:16 -0500 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2005-01-11 19:00:16 -0500 |
| commit | 42f3b4ffb3fedcb70e9ff068ed7160dc6020b8c4 (patch) | |
| tree | ba3d10f448bec63df45dff3bb7f2d6fbd6dcf9c7 /arch | |
| parent | 202758eea20c092bb85d1886898c3816f377d288 (diff) | |
| parent | 90d4436351620bd3861013333aabd152d5492df7 (diff) | |
| download | gem5-42f3b4ffb3fedcb70e9ff068ed7160dc6020b8c4.tar.xz | |
Merge changes.
base/traceflags.py:
Merge extra new CPU flags
cpu/static_inst.hh:
Include all the execute functions in static_inst_impl.hh
--HG--
extra : convert_revision : 78eb753bf709d37400e7c2418bb35d842d7c3f63
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/alpha/isa_desc | 4 | ||||
| -rwxr-xr-x | arch/isa_parser.py | 3 |
2 files changed, 5 insertions, 2 deletions
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index 5154d78d1..fbd4cfe60 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -2480,9 +2480,9 @@ decode OPCODE default Unknown::unknown() { xc->syscall(); }}, IsNonSpeculative); // Read uniq reg into ABI return value register (r0) - 0x9e: rduniq({{ R0 = Runiq; }}); + 0x9e: rduniq({{ R0 = Runiq; }}, IsNonSpeculative); // Write uniq reg with value from ABI arg register (r16) - 0x9f: wruniq({{ Runiq = R16; }}); + 0x9f: wruniq({{ Runiq = R16; }}, IsNonSpeculative); } } #endif diff --git a/arch/isa_parser.py b/arch/isa_parser.py index c0b5131de..7228f99b6 100755 --- a/arch/isa_parser.py +++ b/arch/isa_parser.py @@ -639,6 +639,9 @@ CpuModel('FastCPU', 'fast_cpu_exec.cc', CpuModel('FullCPU', 'full_cpu_exec.cc', '#include "cpu/full_cpu/dyn_inst.hh"', { 'CPU_exec_context': 'DynInst' }) +CpuModel('AlphaFullCPU', 'alpha_full_cpu_exec.cc', + '#include "cpu/beta_cpu/alpha_dyn_inst.hh"', + { 'CPU_exec_context': 'AlphaDynInst<AlphaSimpleImpl>' }) # Expand template with CPU-specific references into a dictionary with # an entry for each CPU model name. The entry key is the model name |