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authorKevin Lim <ktlim@umich.edu>2006-02-16 11:55:28 -0500
committerKevin Lim <ktlim@umich.edu>2006-02-16 11:55:28 -0500
commit485568efa972db7fc27f34708d9bc3a2f19871de (patch)
tree36ce046052a69c7838d4afc50712883e5c7f33a3 /arch
parent2d04f186748c70b3d8afecd39b94436c33848d93 (diff)
downloadgem5-485568efa972db7fc27f34708d9bc3a2f19871de.tar.xz
Fixes to handle generating the initiateAcc and completeAcc functions a little more cleanly.
arch/alpha/isa/mem.isa: Avoid explicitly declaring the Mem variable. Instead break up the code blocks used to generate the initiate and complete functions. The templates reflect which operands need to be declared for each function (src, dest, or both). Loads use both the EA code and mem acc code for the initiate, and memacc code and postacc code for the complete. Stores use both the EA code and mem acc code for the initiate, and only post acc code for the complete. arch/isa_parser.py: Remove hack for mem ops. --HG-- extra : convert_revision : a367797a2cb698762bfc27be1da00bcbe9367150
Diffstat (limited to 'arch')
-rw-r--r--arch/alpha/isa/mem.isa51
-rwxr-xr-xarch/isa_parser.py4
2 files changed, 35 insertions, 20 deletions
diff --git a/arch/alpha/isa/mem.isa b/arch/alpha/isa/mem.isa
index 1889daefc..37d0dcf14 100644
--- a/arch/alpha/isa/mem.isa
+++ b/arch/alpha/isa/mem.isa
@@ -288,7 +288,6 @@ def template LoadInitiateAcc {{
{
Addr EA;
Fault fault = No_Fault;
- %(mem_acc_type)s Mem = 0;
%(fp_enable_check)s;
%(op_src_decl)s;
@@ -310,9 +309,9 @@ def template LoadCompleteAcc {{
Trace::InstRecord *traceData) const
{
Fault fault = No_Fault;
- %(mem_acc_type)s Mem = 0;
%(fp_enable_check)s;
+ %(op_src_decl)s;
%(op_dest_decl)s;
memcpy(&Mem, data, sizeof(Mem));
@@ -409,10 +408,10 @@ def template StoreInitiateAcc {{
Addr EA;
Fault fault = No_Fault;
uint64_t write_result = 0;
- %(mem_acc_type)s Mem = 0;
%(fp_enable_check)s;
%(op_src_decl)s;
+ %(op_dest_decl)s;
%(op_rd)s;
%(ea_code)s;
@@ -501,17 +500,7 @@ def template MiscInitiateAcc {{
Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- Addr EA;
- Fault fault = No_Fault;
-
- %(fp_enable_check)s;
- %(op_decl)s;
- %(op_rd)s;
- %(ea_code)s;
-
- if (fault == No_Fault) {
- %(memacc_code)s;
- }
+ panic("Misc instruction does not support split access method!");
return No_Fault;
}
@@ -523,6 +512,8 @@ def template MiscCompleteAcc {{
%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
+ panic("Misc instruction does not support split access method!");
+
return No_Fault;
}
}};
@@ -584,6 +575,34 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
# for the post-access code.
memacc_iop.postacc_code = postacc_cblk.code
+ # generate InstObjParams for InitiateAcc, CompleteAcc object
+ # The code used depends on the template being used
+ if (exec_template_base == 'Load'):
+ initiateacc_cblk = CodeBlock(ea_code + memacc_code)
+ completeacc_cblk = CodeBlock(memacc_code + postacc_code)
+ elif (exec_template_base == 'Store'):
+ initiateacc_cblk = CodeBlock(ea_code + memacc_code)
+ completeacc_cblk = CodeBlock(postacc_code)
+ else:
+ initiateacc_cblk = ''
+ completeacc_cblk = ''
+
+ initiateacc_iop = InstObjParams(name, Name, base_class, initiateacc_cblk,
+ inst_flags)
+
+ completeacc_iop = InstObjParams(name, Name, base_class, completeacc_cblk,
+ inst_flags)
+
+ if (exec_template_base == 'Load'):
+ initiateacc_iop.ea_code = ea_cblk.code
+ initiateacc_iop.memacc_code = memacc_cblk.code
+ completeacc_iop.memacc_code = memacc_cblk.code
+ completeacc_iop.postacc_code = postacc_cblk.code
+ elif (exec_template_base == 'Store'):
+ initiateacc_iop.ea_code = ea_cblk.code
+ initiateacc_iop.memacc_code = memacc_cblk.code
+ completeacc_iop.postacc_code = postacc_cblk.code
+
# generate InstObjParams for unified execution
cblk = CodeBlock(ea_code + memacc_code + postacc_code)
iop = InstObjParams(name, Name, base_class, cblk, inst_flags)
@@ -611,8 +630,8 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
EACompExecute.subst(ea_iop)
+ memAccExecTemplate.subst(memacc_iop)
+ fullExecTemplate.subst(iop)
- + initiateAccTemplate.subst(iop)
- + completeAccTemplate.subst(iop))
+ + initiateAccTemplate.subst(initiateacc_iop)
+ + completeAccTemplate.subst(completeacc_iop))
}};
diff --git a/arch/isa_parser.py b/arch/isa_parser.py
index 96d3e8438..bcef77ddf 100755
--- a/arch/isa_parser.py
+++ b/arch/isa_parser.py
@@ -1149,10 +1149,6 @@ class Operand(object):
self.constructor = self.makeConstructor()
self.op_decl = self.makeDecl()
- if self.isMem():
- self.is_src = ''
- self.is_dest = ''
-
if self.is_src:
self.op_rd = self.makeRead()
self.op_src_decl = self.makeDecl()