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authorKevin Lim <ktlim@umich.edu>2005-02-25 18:00:49 -0500
committerKevin Lim <ktlim@umich.edu>2005-02-25 18:00:49 -0500
commit5c4714c1a91680a0253f866958a9db80cd8decb2 (patch)
tree6c73396b0418a7d8576c289e31839e8e664bbca0 /arch
parente8a564b0fdd8c5b6ae8f73613e3ad25005556ec5 (diff)
downloadgem5-5c4714c1a91680a0253f866958a9db80cd8decb2.tar.xz
Initial light-weight OoO CPU checkin, along with gcc-3.4 fixes.
SConscript: Include new files. arch/alpha/isa_desc: Make the eaCompPtr and memAccPtr non-const so that execute() can be called on them. arch/alpha/isa_traits.hh: Add enum for total number of data registers. arch/isa_parser.py: base/traceflags.py: Include new light-weight OoO CPU model. cpu/base_dyn_inst.cc: cpu/base_dyn_inst.hh: Changes to abstract more away from the base dyn inst class. cpu/beta_cpu/2bit_local_pred.cc: cpu/beta_cpu/2bit_local_pred.hh: cpu/beta_cpu/tournament_pred.cc: cpu/beta_cpu/tournament_pred.hh: Remove redundant SatCounter class. cpu/beta_cpu/alpha_dyn_inst.cc: cpu/beta_cpu/alpha_full_cpu.cc: cpu/beta_cpu/alpha_full_cpu.hh: cpu/beta_cpu/bpred_unit.cc: cpu/beta_cpu/inst_queue.cc: cpu/beta_cpu/mem_dep_unit.cc: cpu/beta_cpu/ras.cc: cpu/beta_cpu/rename_map.cc: cpu/beta_cpu/rename_map.hh: cpu/beta_cpu/rob.cc: Fix for gcc-3.4 cpu/beta_cpu/alpha_dyn_inst.hh: cpu/beta_cpu/alpha_dyn_inst_impl.hh: Fixes for gcc-3.4. Include more variables and functions that are specific to AlphaDynInst which were once in BaseDynInst. cpu/beta_cpu/alpha_full_cpu_builder.cc: Make params match the current params inherited from BaseCPU. cpu/beta_cpu/alpha_full_cpu_impl.hh: Fixes for gcc-3.4 cpu/beta_cpu/full_cpu.cc: Use new params pointer in BaseCPU. Fix for gcc-3.4. cpu/beta_cpu/full_cpu.hh: Use new params class from BaseCPU. cpu/beta_cpu/iew_impl.hh: Remove unused function. cpu/simple_cpu/simple_cpu.cc: Remove unused global variable. cpu/static_inst.hh: Include OoODynInst for new lightweight OoO CPU --HG-- extra : convert_revision : 34d9f2e64ca0313377391e0d059bf09c040286fa
Diffstat (limited to 'arch')
-rw-r--r--arch/alpha/isa_desc8
-rw-r--r--arch/alpha/isa_traits.hh4
-rwxr-xr-xarch/isa_parser.py3
3 files changed, 11 insertions, 4 deletions
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index e7d0d68ce..1e92033dc 100644
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -738,9 +738,9 @@ output header {{
/// Memory request flags. See mem_req_base.hh.
unsigned memAccessFlags;
/// Pointer to EAComp object.
- const StaticInstPtr<AlphaISA> eaCompPtr;
+ StaticInstPtr<AlphaISA> eaCompPtr;
/// Pointer to MemAcc object.
- const StaticInstPtr<AlphaISA> memAccPtr;
+ StaticInstPtr<AlphaISA> memAccPtr;
/// Constructor
Memory(const char *mnem, MachInst _machInst, OpClass __opClass,
@@ -755,8 +755,8 @@ output header {{
public:
- const StaticInstPtr<AlphaISA> &eaCompInst() const { return eaCompPtr; }
- const StaticInstPtr<AlphaISA> &memAccInst() const { return memAccPtr; }
+ StaticInstPtr<AlphaISA> &eaCompInst() { return eaCompPtr; }
+ StaticInstPtr<AlphaISA> &memAccInst() { return memAccPtr; }
};
/**
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index ff3da1502..bf184b875 100644
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -148,6 +148,10 @@ static const Addr PageOffset = PageBytes - 1;
NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
};
+ enum {
+ TotalDataRegs = NumIntRegs + NumFloatRegs
+ };
+
typedef union {
IntReg intreg;
FloatReg fpreg;
diff --git a/arch/isa_parser.py b/arch/isa_parser.py
index 8187cf188..5e0267c9e 100755
--- a/arch/isa_parser.py
+++ b/arch/isa_parser.py
@@ -642,6 +642,9 @@ CpuModel('FullCPU', 'full_cpu_exec.cc',
CpuModel('AlphaFullCPU', 'alpha_full_cpu_exec.cc',
'#include "cpu/beta_cpu/alpha_dyn_inst.hh"',
{ 'CPU_exec_context': 'AlphaDynInst<AlphaSimpleImpl>' })
+CpuModel('OoOCPU', 'ooo_cpu_exec.cc',
+ '#include "cpu/ooo_cpu/ooo_dyn_inst.hh"',
+ { 'CPU_exec_context': 'OoODynInst<OoOImpl>' })
# Expand template with CPU-specific references into a dictionary with
# an entry for each CPU model name. The entry key is the model name