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authorKevin Lim <ktlim@umich.edu>2005-05-03 10:56:47 -0400
committerKevin Lim <ktlim@umich.edu>2005-05-03 10:56:47 -0400
commit61d95de4c886911fa0b7dc9d587ffe5b292b739e (patch)
treed70531683cfb9bdb7ab967a99fbb3d6e0c34814f /arch
parent6191d3e4443b5337232a238a3a0dd5d11249e223 (diff)
downloadgem5-61d95de4c886911fa0b7dc9d587ffe5b292b739e.tar.xz
Large update of several parts of my code. The most notable change is the inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version.
SConscript: arch/isa_parser.py: cpu/base_dyn_inst.cc: Remove OOO CPU stuff. arch/alpha/faults.hh: Add fake memory fault. This will be removed eventually. arch/alpha/isa_desc: Change EA comp and Mem accessor to be const StaticInstPtrs. cpu/base_dyn_inst.hh: Update read/write calls to use load queue and store queue indices. cpu/beta_cpu/alpha_dyn_inst.hh: Change to const StaticInst in the register accessors. cpu/beta_cpu/alpha_dyn_inst_impl.hh: Update syscall code with thread numbers. cpu/beta_cpu/alpha_full_cpu.hh: Alter some of the full system code so it will compile without errors. cpu/beta_cpu/alpha_full_cpu_builder.cc: Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters. cpu/beta_cpu/alpha_full_cpu_impl.hh: Update some of the full system code so it compiles. cpu/beta_cpu/alpha_params.hh: cpu/beta_cpu/fetch_impl.hh: Remove asid. cpu/beta_cpu/comm.hh: Remove global history field. cpu/beta_cpu/commit.hh: Comment out rename map. cpu/beta_cpu/commit_impl.hh: Update some of the full system code so it compiles. Also change it so that it handles memory instructions properly. cpu/beta_cpu/cpu_policy.hh: Removed IQ from the IEW template parameter to make it more uniform. cpu/beta_cpu/decode.hh: Add debug function. cpu/beta_cpu/decode_impl.hh: Slight updates for decode in the case where it causes a squash. cpu/beta_cpu/fetch.hh: cpu/beta_cpu/rob.hh: Comment out unneccessary code. cpu/beta_cpu/full_cpu.cc: Changed some of the full system code so it compiles. Updated exec contexts and so forth to hopefully make multithreading easier. cpu/beta_cpu/full_cpu.hh: Updated some of the full system code to make it compile. cpu/beta_cpu/iew.cc: Removed IQ from template parameter to IEW. cpu/beta_cpu/iew.hh: Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue. cpu/beta_cpu/iew_impl.hh: New handling of memory instructions through the Load/Store queue. cpu/beta_cpu/inst_queue.hh: Updated comment. cpu/beta_cpu/inst_queue_impl.hh: Slightly different handling of memory instructions due to Load/Store queue. cpu/beta_cpu/regfile.hh: Updated full system code so it compiles. cpu/beta_cpu/rob_impl.hh: Moved some code around; no major functional changes. cpu/ooo_cpu/ooo_cpu.hh: Slight updates to OOO CPU; still does not work. cpu/static_inst.hh: Remove OOO CPU stuff. Change ea comp and mem acc to return const StaticInst. kern/kernel_stats.hh: Extra forward declares added due to compile error. --HG-- extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
Diffstat (limited to 'arch')
-rw-r--r--arch/alpha/faults.hh1
-rw-r--r--arch/alpha/isa_desc12
-rwxr-xr-xarch/isa_parser.py3
3 files changed, 7 insertions, 9 deletions
diff --git a/arch/alpha/faults.hh b/arch/alpha/faults.hh
index 45ac122dc..a49a1c4f0 100644
--- a/arch/alpha/faults.hh
+++ b/arch/alpha/faults.hh
@@ -47,6 +47,7 @@ enum Fault {
Fen_Fault, // FP not-enabled fault
Pal_Fault, // call_pal S/W interrupt
Integer_Overflow_Fault,
+ Fake_Mem_Fault,
Num_Faults // number of faults
};
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index 904af3ef0..0e07400d3 100644
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -744,9 +744,9 @@ output header {{
/// Memory request flags. See mem_req_base.hh.
unsigned memAccessFlags;
/// Pointer to EAComp object.
- StaticInstPtr<AlphaISA> eaCompPtr;
+ const StaticInstPtr<AlphaISA> eaCompPtr;
/// Pointer to MemAcc object.
- StaticInstPtr<AlphaISA> memAccPtr;
+ const StaticInstPtr<AlphaISA> memAccPtr;
/// Constructor
Memory(const char *mnem, MachInst _machInst, OpClass __opClass,
@@ -762,8 +762,8 @@ output header {{
public:
- StaticInstPtr<AlphaISA> &eaCompInst() { return eaCompPtr; }
- StaticInstPtr<AlphaISA> &memAccInst() { return memAccPtr; }
+ const StaticInstPtr<AlphaISA> &eaCompInst() const { return eaCompPtr; }
+ const StaticInstPtr<AlphaISA> &memAccInst() const { return memAccPtr; }
};
/**
@@ -2539,9 +2539,9 @@ decode OPCODE default Unknown::unknown() {
xc->syscall();
}}, IsNonSpeculative);
// Read uniq reg into ABI return value register (r0)
- 0x9e: rduniq({{ R0 = Runiq; }}, IsNonSpeculative);
+ 0x9e: rduniq({{ R0 = Runiq; }});
// Write uniq reg with value from ABI arg register (r16)
- 0x9f: wruniq({{ Runiq = R16; }}, IsNonSpeculative);
+ 0x9f: wruniq({{ Runiq = R16; }});
}
}
#endif
diff --git a/arch/isa_parser.py b/arch/isa_parser.py
index 5e0267c9e..8187cf188 100755
--- a/arch/isa_parser.py
+++ b/arch/isa_parser.py
@@ -642,9 +642,6 @@ CpuModel('FullCPU', 'full_cpu_exec.cc',
CpuModel('AlphaFullCPU', 'alpha_full_cpu_exec.cc',
'#include "cpu/beta_cpu/alpha_dyn_inst.hh"',
{ 'CPU_exec_context': 'AlphaDynInst<AlphaSimpleImpl>' })
-CpuModel('OoOCPU', 'ooo_cpu_exec.cc',
- '#include "cpu/ooo_cpu/ooo_dyn_inst.hh"',
- { 'CPU_exec_context': 'OoODynInst<OoOImpl>' })
# Expand template with CPU-specific references into a dictionary with
# an entry for each CPU model name. The entry key is the model name