Merge zizzer:/bk/multiarch

into  zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/multiarch-m5

--HG--
extra : convert_revision : f3502f293f6ea44b5cf209ce2a935a25bca6054f

1 files changed, 11 insertions, 1 deletions

diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa
index 9994acd0b..7d770c554 100644
--- a/arch/mips/isa/decoder.isa
+++ b/arch/mips/isa/decoder.isa
@@ -30,7 +30,17 @@ decode OPCODE_HI default Unknown::unknown() {
                     //Table A-3 Note: "1. Specific encodings of the rt, rd, and sa fields
                     //are used to distinguish among the SLL, NOP, SSNOP and EHB functions."
 
-                    0x0: sll({{ Rd = Rt.uw << SA; }});
+                    0x0: decode RS {
+                        0x0: decode RT default BasicOp::sll({{ Rd = Rt.uw << SA; }}) {
+                            0x0: decode RD{
+                                0x0: decode HINT {
+                                    0x0:nop({{}});
+                                    0x1:ssnop({{}});
+                                    0x3:ehb({{}});
+                                }
+                            }
+                        }
+                    }
 
                     0x2: decode SRL {
                         0: srl({{ Rd = Rt.uw >> SA; }});