diff options
| author | Steve Reinhardt <stever@eecs.umich.edu> | 2003-10-28 09:09:45 -0800 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2003-10-28 09:09:45 -0800 |
| commit | 18205206972932a236d0bf4f427918b57f9857f0 (patch) | |
| tree | 275ec2898ae04aa891015637075092e671b7b793 /arch | |
| parent | cec7f73abf841a65bdce38d6eb67a643e4879335 (diff) | |
| download | gem5-18205206972932a236d0bf4f427918b57f9857f0.tar.xz | |
Clean up a few spots where we weren't handling of misspeculation correctly.
arch/alpha/ev5.cc:
Don't call kernelStats.hwrei() or system->breakpoint() on misspeculated paths.
arch/alpha/isa_desc:
Don't write reegs.intrflag, do Annotate::Callpal, or call xc->syscall
on misspeculated paths.
--HG--
extra : convert_revision : e73b96fbe4ac5be85fb20aa218fd05fd56d5b2f3
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/alpha/ev5.cc | 8 | ||||
| -rw-r--r-- | arch/alpha/isa_desc | 17 |
2 files changed, 17 insertions, 8 deletions
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index ff1ecc4bf..826a1ab02 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -168,11 +168,11 @@ ExecContext::hwrei() if (!PC_PAL(regs.pc)) return Unimplemented_Opcode_Fault; - kernelStats.hwrei(); - - regs.npc = ipr[AlphaISA::IPR_EXC_ADDR]; + setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]); if (!misspeculating()) { + kernelStats.hwrei(); + if ((ipr[AlphaISA::IPR_EXC_ADDR] & 1) == 0) AlphaISA::swap_palshadow(®s, false); @@ -560,7 +560,7 @@ ExecContext::simPalCheck(int palFunc) case PAL::bpt: case PAL::bugchk: - if (system->breakpoint()) + if (!misspeculating() && system->breakpoint()) return false; break; } diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index ac6934fac..75f765029 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -2322,11 +2322,15 @@ decode OPCODE default Unknown::unknown() { format BasicOperate { 0xe000: rc({{ Ra = xc->regs.intrflag; - xc->regs.intrflag = 0; + if (!xc->misspeculating()) { + xc->regs.intrflag = 0; + } }}, No_OpClass); 0xf000: rs({{ Ra = xc->regs.intrflag; - xc->regs.intrflag = 1; + if (!xc->misspeculating()) { + xc->regs.intrflag = 1; + } }}, No_OpClass); } #else @@ -2343,7 +2347,9 @@ decode OPCODE default Unknown::unknown() { // on this PAL call (including maybe suppress it) bool dopal = xc->simPalCheck(palFunc); - Annotate::Callpal(xc, palFunc); + if (!xc->misspeculating()) { + Annotate::Callpal(xc, palFunc); + } if (dopal) { if (!xc->misspeculating()) { @@ -2360,7 +2366,10 @@ decode OPCODE default Unknown::unknown() { if (!xc->misspeculating()) SimExit("halt instruction encountered"); }}); - 0x83: callsys({{ xc->syscall(); }}); + 0x83: callsys({{ + if (!xc->misspeculating()) + xc->syscall(); + }}); // Read uniq reg into ABI return value register (r0) 0x9e: rduniq({{ R0 = Runiq; }}); // Write uniq reg with value from ABI arg register (r16) |