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authorSteve Reinhardt <stever@eecs.umich.edu>2004-05-18 22:09:13 -0700
committerSteve Reinhardt <stever@eecs.umich.edu>2004-05-18 22:09:13 -0700
commit27a6e8258dabef233bc1681649b871bf150878ed (patch)
treed054d7b3aae65dcc17f36108eb163d287277502d /arch
parent4c55d26e664f870d56889097939569c4b07c6de2 (diff)
downloadgem5-27a6e8258dabef233bc1681649b871bf150878ed.tar.xz
Add a level of indirection to the register accessors used in
instruction execute methods. Register i now means the instruction's i'th src (or dest) operand, not architectural register i. Current models that use the architectural reg index can look that up easily in the instruction object. Future models that do register renaming should find this much simpler to deal with. arch/isa_parser.py: Generate register accessors with an extra level of indirection. cpu/simple_cpu/simple_cpu.hh: Modify register accessors to use an extra level of indirection. --HG-- extra : convert_revision : f4c7d6bfa92fb2ea6251f31ee368809c3643f08f
Diffstat (limited to 'arch')
-rwxr-xr-xarch/isa_parser.py10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/isa_parser.py b/arch/isa_parser.py
index 621720709..7f77241be 100755
--- a/arch/isa_parser.py
+++ b/arch/isa_parser.py
@@ -1057,10 +1057,10 @@ class IntRegOperandTraits(OperandTraits):
if (type == 'float' or type == 'double'):
error(0, 'Attempt to read integer register as FP')
if (size == self.dflt_size):
- return '%s = xc->readIntReg(_srcRegIdx[%d]);\n' % \
+ return '%s = xc->readIntReg(this, %d);\n' % \
(op_desc.munged_name, op_desc.src_reg_idx)
else:
- return '%s = bits(xc->readIntReg(_srcRegIdx[%d]), %d, 0);\n' % \
+ return '%s = bits(xc->readIntReg(this, %d), %d, 0);\n' % \
(op_desc.munged_name, op_desc.src_reg_idx, size-1)
def makeWrite(self, op_desc):
@@ -1074,7 +1074,7 @@ class IntRegOperandTraits(OperandTraits):
wb = '''
{
%s final_val = %s;
- xc->setIntReg(_destRegIdx[%d], final_val);\n
+ xc->setIntReg(this, %d, final_val);\n
if (traceData) { traceData->setData(final_val); }
}''' % (self.dflt_type, final_val, op_desc.dest_reg_idx)
return wb
@@ -1107,7 +1107,7 @@ class FloatRegOperandTraits(OperandTraits):
func = 'readFloatRegInt'
if (size != self.dflt_size):
bit_select = 1
- base = 'xc->%s(_srcRegIdx[%d] - FP_Base_DepTag)' % \
+ base = 'xc->%s(this, %d)' % \
(func, op_desc.src_reg_idx)
if bit_select:
return '%s = bits(%s, %d, 0);\n' % \
@@ -1130,7 +1130,7 @@ class FloatRegOperandTraits(OperandTraits):
wb = '''
{
%s final_val = %s;
- xc->%s(_destRegIdx[%d] - FP_Base_DepTag, final_val);\n
+ xc->%s(this, %d, final_val);\n
if (traceData) { traceData->setData(final_val); }
}''' % (type, final_val, func, op_desc.dest_reg_idx)
return wb