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authorNathan Binkert <binkertn@umich.edu>2004-02-09 09:06:20 -0500
committerNathan Binkert <binkertn@umich.edu>2004-02-09 09:06:20 -0500
commit411d5497fa2bd28c9cf4ac1fccf806ee8a1ff33d (patch)
tree68f152cd40031ce29bdacbbed6e8a1321cc7efc5 /arch
parent6ece3a7e5985e4bf5ff1f8eb9d0680647d00c4c6 (diff)
downloadgem5-411d5497fa2bd28c9cf4ac1fccf806ee8a1ff33d.tar.xz
Add that one IPR memory space address that we keep seeing
--HG-- extra : convert_revision : 81b365ac9ca8b33cae99107e5b1900f7c46f0866
Diffstat (limited to 'arch')
-rw-r--r--arch/alpha/alpha_memory.cc13
1 files changed, 11 insertions, 2 deletions
diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc
index 0f9ad2cfc..00e97250f 100644
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/alpha_memory.cc
@@ -90,8 +90,17 @@ AlphaTlb::checkCacheability(MemReqPtr &req)
if (req->paddr & PA_UNCACHED_BIT) {
if (PA_IPR_SPACE(req->paddr)) {
// IPR memory space not implemented
- if (!req->xc->misspeculating())
- panic("IPR memory space not implemented! PA=%x\n", req->paddr);
+ if (!req->xc->misspeculating()) {
+ switch (req->paddr) {
+ case 0xFFFFF00188:
+ req->data = 0;
+ break;
+
+ default:
+ panic("IPR memory space not implemented! PA=%x\n",
+ req->paddr);
+ }
+ }
} else {
// mark request as uncacheable
req->flags |= UNCACHEABLE;