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| author | Steve Reinhardt <stever@eecs.umich.edu> | 2004-02-09 00:22:43 -0800 |
|---|---|---|
| committer | Steve Reinhardt <stever@eecs.umich.edu> | 2004-02-09 00:22:43 -0800 |
| commit | d7b7363444614a4e07676151604ce9600bad1169 (patch) | |
| tree | 723f703733aa064e9b065a7ddc84dcb4502ac49f /arch | |
| parent | b6ff600bcae2d1e816d0e409c1638a15e207695b (diff) | |
| download | gem5-d7b7363444614a4e07676151604ce9600bad1169.tar.xz | |
Add support for memory barriers.
arch/alpha/isa_desc:
Add cache port bindings for mb & wmb.
--HG--
extra : convert_revision : 72f76150fe471d0dc97bd41598cad4d86a035e39
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/alpha/isa_desc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc index d4636f609..75b2f4138 100644 --- a/arch/alpha/isa_desc +++ b/arch/alpha/isa_desc @@ -2362,8 +2362,8 @@ decode OPCODE default Unknown::unknown() { // them the same though. 0x0000: trapb({{ }}, IsSerializing, No_OpClass); 0x0400: excb({{ }}, IsSerializing, No_OpClass); - 0x4000: mb({{ }}, IsMemBarrier); - 0x4400: wmb({{ }}, IsWriteBarrier); + 0x4000: mb({{ }}, IsMemBarrier, RdPort); + 0x4400: wmb({{ }}, IsWriteBarrier, WrPort); } #ifdef FULL_SYSTEM |