Pushed ev5.hh out of the non-alpha code.

arch/SConscript:
    ev5 should now be contained within alpha specific code.
arch/alpha/ev5.cc:
arch/alpha/isa_traits.hh:
    Added getInstAsid and getDataAsid functions. These should be removed when the SimpleScalar cpu model is removed.
arch/sparc/isa_traits.hh:
    Added getInstAsid and getDataAsid functions. These should be removed when the SimpleScalar cpu model is removed. Also made some small fixes.
cpu/o3/alpha_cpu.hh:
    Added typedefs which are required now that there isn't a using namespace EV5.
cpu/o3/alpha_cpu_impl.hh:
    Some small changes so that ev5.hh isn't needed directly.
cpu/o3/cpu.hh:
    Removed including ev5.hh, and pushed retrieving the Asid into the MiscRegFile.
cpu/o3/regfile.hh:
    Removed the include of ev5.hh, using namespace EV5, and the now redundant ipr array.

--HG--
extra : convert_revision : 5ef8f69435a3a888a3f06d0095d89326dafb33fd

4 files changed, 29 insertions, 3 deletions

diff --git a/arch/SConscript b/arch/SConscript
index 380cda307..0533261a2 100644
--- a/arch/SConscript
+++ b/arch/SConscript
@@ -52,7 +52,6 @@ isa_switch_hdrs = Split('''
 	stacktrace.hh
 	vtophys.hh
 	faults.hh
-	ev5.hh
         ''')
 
 # Generate the header.  target[0] is the full path of the output
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index e313c1a1c..47ada6de6 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -152,6 +152,18 @@ ExecContext::hwrei()
     return NoFault;
 }
 
+int
+AlphaISA::MiscRegFile::getInstAsid()
+{
+    return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
+}
+
+int
+AlphaISA::MiscRegFile::getDataAsid()
+{
+    return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
+}
+
 void
 AlphaISA::MiscRegFile::clearIprs()
 {
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index 742539e89..be6d5111d 100644
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -166,6 +166,11 @@ extern const int reg_redir[NumIntRegs];
       public:
         MiscReg readReg(int misc_reg);
 
+        //These functions should be removed once the simplescalar cpu model
+        //has been replaced.
+        int getInstAsid();
+        int getDataAsid();
+
         MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc);
 
         Fault setReg(int misc_reg, const MiscReg &val);
diff --git a/arch/sparc/isa_traits.hh b/arch/sparc/isa_traits.hh
index 0fdac1662..73daae8a9 100644
--- a/arch/sparc/isa_traits.hh
+++ b/arch/sparc/isa_traits.hh
@@ -57,7 +57,7 @@ class StaticInstPtr;
 namespace SparcISA
 {
     typedef uint32_t MachInst;
-    typedef uint64_t Addr;
+    typedef uint64_t ExtMachInst;
     typedef uint8_t  RegIndex;
 
     enum
@@ -179,7 +179,7 @@ namespace SparcISA
     // The control registers, broken out into fields
     class MiscRegFile
     {
-      public:
+      private:
         union
         {
             uint16_t pstate;		// Process State Register
@@ -365,6 +365,16 @@ namespace SparcISA
             } fprsFields;
         };
 
+      public:
+        MiscReg readReg(int misc_reg);
+
+        MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc);
+
+        Fault setReg(int misc_reg, const MiscReg &val);
+
+        Fault setRegWithEffect(int misc_reg, const MiscReg &val,
+                               ExecContext *xc);
+
         void serialize(std::ostream & os);
 
         void unserialize(Checkpoint * cp, std::string & section);