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authorAli Saidi <saidi@eecs.umich.edu>2006-03-16 23:09:01 -0500
committerAli Saidi <saidi@eecs.umich.edu>2006-03-16 23:09:01 -0500
commitcf942425393dbd7ac3d05a9c94aab5140d0bf617 (patch)
tree782f40e1f4bebed7651b2234d6f26988963db543 /arch
parentfc5d25bdb63bd47e51a47111258d9edf1232a23b (diff)
downloadgem5-cf942425393dbd7ac3d05a9c94aab5140d0bf617.tar.xz
clean up condition codes a little bit
put back in Tcc code that was deleted in last merge arch/sparc/isa/bitfields.isa: clean up condition codes a little bit --HG-- extra : convert_revision : c554fd5c3ee8cfd6643f69f8351124a7a4b5d9fa
Diffstat (limited to 'arch')
-rw-r--r--arch/sparc/isa/bitfields.isa12
-rw-r--r--arch/sparc/isa/decoder.isa40
2 files changed, 30 insertions, 22 deletions
diff --git a/arch/sparc/isa/bitfields.isa b/arch/sparc/isa/bitfields.isa
index 237f0fa64..988f067c6 100644
--- a/arch/sparc/isa/bitfields.isa
+++ b/arch/sparc/isa/bitfields.isa
@@ -7,13 +7,11 @@
// simply defined alphabetically
def bitfield A <29>;
-def bitfield CC02 <20>;
-def bitfield CC03 <25>;
-def bitfield CC04 <11>;
-def bitfield CC12 <21>;
-def bitfield CC13 <26>;
-def bitfield CC14 <12>;
-def bitfield CC2 <18>;
+def bitfield BPCC <21:20>; // for BPcc & FBPcc
+def bitfield FCMPCC <26:56>; // for FCMP & FCMPEa
+def bitflied FMOVCC <13:11>; // for FMOVcc
+def bitfield CC <12:11>; // for MOVcc & Tcc
+def bitfierd MOVCC3 <18>; // also for MOVcc
def bitfield CMASK <6:4>;
def bitfield COND2 <28:25>;
def bitfield COND4 <17:14>;
diff --git a/arch/sparc/isa/decoder.isa b/arch/sparc/isa/decoder.isa
index 14280ef12..2b5296eed 100644
--- a/arch/sparc/isa/decoder.isa
+++ b/arch/sparc/isa/decoder.isa
@@ -10,7 +10,7 @@ decode OP default Unknown::unknown()
//Throw an illegal instruction acception
0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
0x1: Branch::bpcc({{
- switch((CC12 << 1) | CC02)
+ switch(BPCC)
{
case 1:
case 3:
@@ -387,7 +387,7 @@ decode OP default Unknown::unknown()
}
0x2B: BasicOperate::flushw({{\\window toilet}}); //FLUSHW
0x2C: movcc({{
- ccBank = (CC24 << 2) | (CC14 << 1) | (CC04 << 0);
+ ccBank = (MOVCC3 << 2) | CC;
switch(ccBank)
{
case 0: case 1: case 2: case 3:
@@ -511,20 +511,30 @@ decode OP default Unknown::unknown()
0x38: Branch::jmpl({{//Stuff}}); //JMPL
0x39: Branch::return({{//Other Stuff}}); //RETURN
- 0x3A: decode CC04
+ 0x3A: decode CC
{
- // If CC04 == 1, it's an illegal instruction
- 0x0: decode CC14
- {
- 0x0: Trap::tcci({{
- if(passesCondition(ccr_icc, machInst<25:28>))
- fault = new TrapInstruction;
- }});
- 0x1: Trap::tccx({{
- if(passesCondition(ccr_xcc, machInst<25:28>))
- fault = new TrapInstruction;
- }});
- }
+ 0x0: Trap::tcci({{
+#if FULL_SYSTEM
+ fault = new TrapInstruction;
+#else
+ if(passesCondition(ccr_icc, machInst<25:28>))
+ // At least glibc only uses trap 0,
+ // solaris/sunos may use others
+ assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0);
+ xc->syscall();
+#endif
+ }});
+ 0x2: Trap::tccx({{
+#if FULL_SYSTEM
+ fault = new TrapInstruction;
+#else
+ if(passesCondition(ccr_xcc, machInst<25:28>))
+ // At least glibc only uses trap 0,
+ // solaris/sunos may use others
+ assert((I ? Rs1 + Rs2 : Rs1 + SW_TRAP) == 0);
+ xc->syscall();
+#endif
+ }});
}
0x3B: BasicOperate::flush({{//Lala}}); //FLUSH
0x3C: BasicOperate::save({{//leprechauns); //SAVE