Merge m5.eecs.umich.edu:/bk/newmem

into  ewok.(none):/home/gblack/m5/newmem

--HG--
extra : convert_revision : 2db5529a9fbe8c62e57cad05f093c915f9713c67

8 files changed, 32 insertions, 114 deletions

diff --git a/arch/alpha/faults.cc b/arch/alpha/faults.cc
index c8cb9124e..0083aa9f3 100644
--- a/arch/alpha/faults.cc
+++ b/arch/alpha/faults.cc
@@ -105,10 +105,6 @@ FaultName IntegerOverflowFault::_name = "intover";
 FaultVect IntegerOverflowFault::_vect = 0x0501;
 FaultStat IntegerOverflowFault::_count;
 
-FaultName UnimpFault::_name = "Unimplemented Simulator feature";
-FaultVect UnimpFault::_vect = 0x0001;
-FaultStat UnimpFault::_count;
-
 #if FULL_SYSTEM
 
 void AlphaFault::invoke(ExecContext * xc)
@@ -174,12 +170,6 @@ void ItbFault::invoke(ExecContext * xc)
     AlphaFault::invoke(xc);
 }
 
-void UnimpFault::invoke(ExecContext * xc)
-{
-    FaultBase::invoke(xc);
-    panic("Unimpfault: %s\n", panicStr.c_str());
-}
-
 #endif
 
 } // namespace AlphaISA
diff --git a/arch/alpha/faults.hh b/arch/alpha/faults.hh
index 5024c124b..e8ccc6b79 100644
--- a/arch/alpha/faults.hh
+++ b/arch/alpha/faults.hh
@@ -347,26 +347,6 @@ class IntegerOverflowFault : public AlphaFault
     FaultStat & countStat() {return _count;}
 };
 
-class UnimpFault : public AlphaFault
-{
-  private:
-    std::string panicStr;
-    static FaultName _name;
-    static FaultVect _vect;
-    static FaultStat _count;
-  public:
-    UnimpFault(std::string _str)
-        : panicStr(_str)
-    { }
-
-    FaultName name() {return _name;}
-    FaultVect vect() {return _vect;}
-    FaultStat & countStat() {return _count;}
-#if FULL_SYSTEM
-    void invoke(ExecContext * xc);
-#endif
-};
-
 } // AlphaISA namespace
 
 #endif // __FAULTS_HH__
diff --git a/arch/mips/faults.cc b/arch/mips/faults.cc
index a31856f07..1b31dfa69 100644
--- a/arch/mips/faults.cc
+++ b/arch/mips/faults.cc
@@ -98,10 +98,6 @@ FaultName IntegerOverflowFault::_name = "intover";
 FaultVect IntegerOverflowFault::_vect = 0x0501;
 FaultStat IntegerOverflowFault::_count;
 
-FaultName UnimpFault::_name = "Unimplemented Simulator feature";
-FaultVect UnimpFault::_vect = 0x0001;
-FaultStat UnimpFault::_count;
-
 #if FULL_SYSTEM
 
 void MipsFault::invoke(ExecContext * xc)
@@ -129,12 +125,6 @@ void ArithmeticFault::invoke(ExecContext * xc)
     panic("Arithmetic traps are unimplemented!");
 }
 
-void UnimpFault::invoke(ExecContext * xc)
-{
-    FaultBase::invoke(xc);
-    panic("Unimpfault: %s\n", panicStr.c_str());
-}
-
 #endif
 
 } // namespace MipsISA
diff --git a/arch/mips/faults.hh b/arch/mips/faults.hh
index b0d228090..0bdabe29e 100644
--- a/arch/mips/faults.hh
+++ b/arch/mips/faults.hh
@@ -264,26 +264,6 @@ class IntegerOverflowFault : public MipsFault
     FaultStat & countStat() {return _count;}
 };
 
-class UnimpFault : public MipsFault
-{
-  private:
-    std::string panicStr;
-    static FaultName _name;
-    static FaultVect _vect;
-    static FaultStat _count;
-  public:
-    UnimpFault(std::string _str)
-        : panicStr(_str)
-    { }
-
-    FaultName name() {return _name;}
-    FaultVect vect() {return _vect;}
-    FaultStat & countStat() {return _count;}
-#if FULL_SYSTEM
-    void invoke(ExecContext * xc);
-#endif
-};
-
 } // MipsISA namespace
 
 #endif // __FAULTS_HH__
diff --git a/arch/sparc/faults.cc b/arch/sparc/faults.cc
index e83bba800..67a89ab0e 100644
--- a/arch/sparc/faults.cc
+++ b/arch/sparc/faults.cc
@@ -215,11 +215,6 @@ TrapType      TrapInstruction::_baseTrapType = 0x100;
 FaultPriority TrapInstruction::_priority = 16;
 FaultStat     TrapInstruction::_count;
 
-FaultName     UnimpFault::_name = "Unimplemented Simulator feature";
-TrapType      UnimpFault::_trapType = 0x000;
-FaultPriority UnimpFault::_priority = 0;
-FaultStat     UnimpFault::_count;
-
 #if FULL_SYSTEM
 
 void SparcFault::invoke(ExecContext * xc)
@@ -245,12 +240,15 @@ void SparcFault::invoke(ExecContext * xc)
     xc->regs.npc = xc->regs.pc + sizeof(MachInst);*/
 }
 
-void UnimpFault::invoke(ExecContext * xc)
+#endif
+
+#if !FULL_SYSTEM
+
+void TrapInstruction::invoke(ExecContext * xc)
 {
-    panic("Unimpfault: %s\n", panicStr.c_str());
+    xc->syscall(syscall_num);
 }
 
-
 #endif
 
 } // namespace SparcISA
diff --git a/arch/sparc/faults.hh b/arch/sparc/faults.hh
index 87de8daaa..e8fb8dfc5 100644
--- a/arch/sparc/faults.hh
+++ b/arch/sparc/faults.hh
@@ -573,37 +573,19 @@ class TrapInstruction : public EnumeratedFault
     static TrapType _baseTrapType;
     static FaultPriority _priority;
     static FaultStat _count;
+    uint64_t syscall_num;
     TrapType baseTrapType() {return _baseTrapType;}
   public:
-    TrapInstruction(uint32_t n) : EnumeratedFault(n) {;}
+    TrapInstruction(uint32_t n, uint64_t syscall) :
+        EnumeratedFault(n), syscall_num(syscall) {;}
     FaultName name() {return _name;}
     FaultPriority priority() {return _priority;}
     FaultStat & countStat() {return _count;}
-};
-
-class UnimpFault : public SparcFault
-{
-  private:
-    static FaultName _name;
-    static TrapType _trapType;
-    static FaultPriority _priority;
-    static FaultStat _count;
-    std::string panicStr;
-  public:
-    UnimpFault(std::string _str)
-        : panicStr(_str)
-    { }
-
-    FaultName name() {return _name;}
-    TrapType trapType() {return _trapType;}
-    FaultPriority priority() {return _priority;}
-    FaultStat & countStat() {return _count;}
-#if FULL_SYSTEM
+#if !FULL_SYSTEM
     void invoke(ExecContext * xc);
 #endif
 };
 
-
 } // SparcISA namespace
 
 #endif // __FAULTS_HH__
diff --git a/arch/sparc/isa/base.isa b/arch/sparc/isa/base.isa
index cb370a3e7..8ea11b40e 100644
--- a/arch/sparc/isa/base.isa
+++ b/arch/sparc/isa/base.isa
@@ -99,14 +99,16 @@ def template ROrImmDecode {{
 
 let {{
     def splitOutImm(code):
-        matcher = re.compile(r'Rs(?P<rNum>\d)_or_imm(?P<iNum>\d+)')
+        matcher = re.compile(r'Rs(?P<rNum>\d)_or_imm(?P<iNum>\d+)(?P<typeQual>\.\w+)?')
         rOrImmMatch = matcher.search(code)
         if (rOrImmMatch == None):
             return (False, code, '', '', '')
         rString = rOrImmMatch.group("rNum")
+        if (rOrImmMatch.group("typeQual") != None):
+            rString += rOrImmMatch.group("typeQual")
         iString = rOrImmMatch.group("iNum")
         orig_code = code
-        code = matcher.sub('Rs' + rOrImmMatch.group("rNum"), orig_code)
+        code = matcher.sub('Rs' + rString, orig_code)
         imm_code = matcher.sub('imm', orig_code)
         return (True, code, imm_code, rString, iString)
 }};
diff --git a/arch/sparc/isa/decoder.isa b/arch/sparc/isa/decoder.isa
index b9e83afd6..52ca5d7cd 100644
--- a/arch/sparc/isa/decoder.isa
+++ b/arch/sparc/isa/decoder.isa
@@ -119,11 +119,11 @@ decode OP default Unknown::unknown()
                 }
             }});
             0x0F: sdiv({{
-                if(Rs2_or_imm13 == 0)
+                if(Rs2_or_imm13.sdw == 0)
                     fault = new DivisionByZero;
                 else
                 {
-                    Rd.udw = ((YValue << 32) | Rs1.sdw<31:0>) / Rs2_or_imm13;
+                    Rd.udw = ((int64_t)((YValue << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
                     if(Rd.udw<63:31> != 0)
                         Rd.udw = 0x7FFFFFFF;
                     else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
@@ -166,13 +166,13 @@ decode OP default Unknown::unknown()
                 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
             );
             0x1A: umulcc({{
-                uint64_t resTemp, val2 = Rs2_or_imm13;
-                Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
+                uint64_t resTemp;
+                Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
                 YValue = resTemp<63:32>;}},
                 {{0}},{{0}},{{0}},{{0}});
             0x1B: smulcc({{
-                int64_t resTemp, val2 = Rs2_or_imm13;
-                Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>;
+                int64_t resTemp;
+                Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>;
                 YValue = resTemp<63:32>;}},
                 {{0}},{{0}},{{0}},{{0}});
             0x1C: subccc({{
@@ -185,11 +185,11 @@ decode OP default Unknown::unknown()
                 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
             );
             0x1D: udivxcc({{
-                if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
-                else Rd = Rs1.udw / Rs2_or_imm13;}}
+                if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
+                else Rd = Rs1.udw / Rs2_or_imm13.udw;}}
                 ,{{0}},{{0}},{{0}},{{0}});
             0x1E: udivcc({{
-                uint32_t resTemp, val2 = Rs2_or_imm13;
+                uint32_t resTemp, val2 = Rs2_or_imm13.udw;
                 int32_t overflow;
                 if(val2 == 0) fault = new DivisionByZero;
                 else
@@ -205,7 +205,7 @@ decode OP default Unknown::unknown()
                 {{0}}
             );
             0x1F: sdivcc({{
-                int32_t resTemp, val2 = Rs2_or_imm13;
+                int32_t resTemp, val2 = Rs2_or_imm13.sdw;
                 int32_t overflow, underflow;
                 if(val2 == 0) fault = new DivisionByZero;
                 else
@@ -363,8 +363,8 @@ decode OP default Unknown::unknown()
                 }
             }
             0x2D: sdivx({{
-                if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
-                else Rd.sdw = Rs1.sdw / Rs2_or_imm13;
+                if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
+                else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
             }});
             0x2E: decode RS1 {
                 0x0: IntOp::popc({{
@@ -382,12 +382,12 @@ decode OP default Unknown::unknown()
             }
             0x2F: decode RCOND3
             {
-                0x1: movreq({{Rd = (Rs1 == 0) ? Rs2_or_imm10 : Rd;}});
-                0x2: movrle({{Rd = (Rs1 <= 0) ? Rs2_or_imm10 : Rd;}});
-                0x3: movrl({{Rd = (Rs1 < 0) ? Rs2_or_imm10 : Rd;}});
-                0x5: movrne({{Rd = (Rs1 != 0) ? Rs2_or_imm10 : Rd;}});
-                0x6: movrg({{Rd = (Rs1 > 0) ? Rs2_or_imm10 : Rd;}});
-                0x7: movrge({{Rd = (Rs1 >= 0) ? Rs2_or_imm10 : Rd;}});
+                0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
+                0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
+                0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
+                0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
+                0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
+                0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
             }
             0x30: decode RD {
                 0x0: wry({{Y = Rs1 ^ Rs2_or_imm13;}});
@@ -492,10 +492,6 @@ decode OP default Unknown::unknown()
                         xc->syscall(R1);
 #endif
                     }
-                    else
-                    {
-                        DPRINTF(Sparc, "Didn't fire on %s\n", CondTestAbbrev[machInst<25:28>]);
-                    }
                 }});
                 0x2: Trap::tccx({{
                     if(passesCondition(CcrXcc, COND2))