Changed the fault enum into a class, and fixed everything up to work with it. Next, the faults need to be pulled out of all the other code so that they are only used to communicate between the CPU and the ISA.

SConscript:
    The new faults.cc file in sim allocates the system wide faults. When these faults are generated through a function interface in the ISA, this file may go away.
arch/alpha/alpha_memory.cc:
    Changed Fault to Fault * and took the underscores out of fault names.
arch/alpha/alpha_memory.hh:
    Changed Fault to Fault *. Also, added an include for the alpha faults.
arch/alpha/ev5.cc:
    Changed the fault_addr array into a fault_addr function. Once all of the faults can be expected to have the same type, fault_addr can go away completely and the info it provided will come from the fault itself. Also, Fault was changed to Fault *, and underscores were taken out of fault names.
arch/alpha/isa/decoder.isa:
    Changed Fault to Fault * and took the underscores out fault names.
arch/alpha/isa/fp.isa:
    Changed Fault to Fault *, and took the underscores out of fault names.
arch/alpha/isa/main.isa:
    Changed Fault to Fault *, removed underscores from fault names, and made an include of the alpha faults show up in all the generated files.
arch/alpha/isa/mem.isa:
    Changed Fault to Fault * and removed underscores from fault names.
arch/alpha/isa/unimp.isa:
arch/alpha/isa/unknown.isa:
cpu/exec_context.hh:
cpu/ozone/cpu.hh:
cpu/simple/cpu.cc:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/pcidev.hh:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
    Changed Fault to Fault *, and removed underscores from fault names.
arch/alpha/isa_traits.hh:
    Changed the include of arch/alpha/faults.hh to sim/faults.hh, since the alpha faults weren't needed.
cpu/base_dyn_inst.cc:
    Changed Fault to Fault *, and removed underscores from fault names. This file probably shouldn't use the Unimplemented Opcode fault.
cpu/base_dyn_inst.hh:
    Changed Fault to Fault * and took the underscores out of the fault names.
cpu/exec_context.cc:
cpu/o3/alpha_dyn_inst.hh:
cpu/o3/alpha_dyn_inst_impl.hh:
cpu/o3/fetch.hh:
dev/alpha_console.hh:
dev/baddev.hh:
dev/ide_ctrl.hh:
dev/isa_fake.hh:
dev/ns_gige.hh:
dev/pciconfigall.hh:
dev/sinic.hh:
dev/tsunami_cchip.hh:
dev/tsunami_io.hh:
dev/tsunami_pchip.hh:
dev/uart.hh:
dev/uart8250.hh:
    Changed Fault to Fault *.
cpu/o3/alpha_cpu.hh:
    Changed Fault to Fault *, removed underscores from fault names.
cpu/o3/alpha_cpu_impl.hh:
    Changed Fault to Fault *, removed underscores from fault names, and changed the fault_addr array to the fault_addr function. Once all faults are from the ISA, this function will probably go away.
cpu/o3/commit_impl.hh:
cpu/o3/fetch_impl.hh:
dev/baddev.cc:
    Changed Fault to Fault *, and removed underscores from the fault names.
cpu/o3/regfile.hh:
    Added an include for the alpha specific faults which will hopefully go away once the ipr stuff is moved, changed Fault to Fault *, and removed the underscores from fault names.
cpu/simple/cpu.hh:
    Changed Fault to Fault *
dev/ns_gige.cc:
    Changed Fault to Fault *, and removdd underscores from fault names.
dev/sinic.cc:
    Changed Fault to Fault *, and removed the underscores from fault names.
dev/uart8250.cc:
    Chanted Fault to Fault *, and removed underscores from fault names.
kern/kernel_stats.cc:
    Removed underscores from fault names, and from NumFaults.
kern/kernel_stats.hh:
    Changed the predeclaration of Fault from an enum to a class, and changd the "fault" function to work with the classes instead of the enum. Once there are no system wide faults anymore, this code will simplify back to something like it was originally.
sim/faults.cc:
    This allocates the system wide faults.
sim/faults.hh:
    This declares the system wide faults.
sim/syscall_emul.cc:
sim/syscall_emul.hh:
    Removed the underscores from fault names.

--HG--
rename : arch/alpha/faults.cc => sim/faults.cc
rename : arch/alpha/faults.hh => sim/faults.hh
extra : convert_revision : 253d39258237333ae8ec4d8047367cb3ea68569d

12 files changed, 262 insertions, 190 deletions

diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc
index 8dda4d9c4..615ce92a4 100644
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/alpha_memory.cc
@@ -303,7 +303,7 @@ AlphaITB::fault(Addr pc, ExecContext *xc) const
 }
 
 
-Fault
+Fault *
 AlphaITB::translate(MemReqPtr &req) const
 {
     InternalProcReg *ipr = req->xc->regs.ipr;
@@ -312,7 +312,7 @@ AlphaITB::translate(MemReqPtr &req) const
         // strip off PAL PC marker (lsb is 1)
         req->paddr = (req->vaddr & ~3) & PAddrImplMask;
         hits++;
-        return No_Fault;
+        return NoFault;
     }
 
     if (req->flags & PHYSICAL) {
@@ -322,7 +322,7 @@ AlphaITB::translate(MemReqPtr &req) const
         if (!validVirtualAddress(req->vaddr)) {
             fault(req->vaddr, req->xc);
             acv++;
-            return ITB_Acv_Fault;
+            return ItbAcvFault;
         }
 
 
@@ -339,7 +339,7 @@ AlphaITB::translate(MemReqPtr &req) const
                 AlphaISA::mode_kernel) {
                 fault(req->vaddr, req->xc);
                 acv++;
-                return ITB_Acv_Fault;
+                return ItbAcvFault;
             }
 
             req->paddr = req->vaddr & PAddrImplMask;
@@ -360,7 +360,7 @@ AlphaITB::translate(MemReqPtr &req) const
             if (!pte) {
                 fault(req->vaddr, req->xc);
                 misses++;
-                return ITB_Fault_Fault;
+                return ItbPageFault;
             }
 
             req->paddr = (pte->ppn << AlphaISA::PageShift) +
@@ -371,7 +371,7 @@ AlphaITB::translate(MemReqPtr &req) const
                 // instruction access fault
                 fault(req->vaddr, req->xc);
                 acv++;
-                return ITB_Acv_Fault;
+                return ItbAcvFault;
             }
 
             hits++;
@@ -380,11 +380,11 @@ AlphaITB::translate(MemReqPtr &req) const
 
     // check that the physical address is ok (catch bad physical addresses)
     if (req->paddr & ~PAddrImplMask)
-        return Machine_Check_Fault;
+        return MachineCheckFault;
 
     checkCacheability(req);
 
-    return No_Fault;
+    return NoFault;
 }
 
 ///////////////////////////////////////////////////////////////////////
@@ -493,7 +493,7 @@ AlphaDTB::fault(MemReqPtr &req, uint64_t flags) const
     }
 }
 
-Fault
+Fault *
 AlphaDTB::translate(MemReqPtr &req, bool write) const
 {
     RegFile *regs = &req->xc->regs;
@@ -511,7 +511,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
         fault(req, write ? MM_STAT_WR_MASK : 0);
         DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->vaddr,
                 req->size);
-        return Alignment_Fault;
+        return AlignmentFault;
     }
 
     if (pc & 0x1) {
@@ -530,7 +530,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
                   MM_STAT_ACV_MASK);
 
             if (write) { write_acv++; } else { read_acv++; }
-            return DTB_Fault_Fault;
+            return DtbPageFault;
         }
 
         // Check for "superpage" mapping
@@ -547,7 +547,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
                 fault(req, ((write ? MM_STAT_WR_MASK : 0) |
                             MM_STAT_ACV_MASK));
                 if (write) { write_acv++; } else { read_acv++; }
-                return DTB_Acv_Fault;
+                return DtbAcvFault;
             }
 
             req->paddr = req->vaddr & PAddrImplMask;
@@ -575,7 +575,7 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
                 fault(req, (write ? MM_STAT_WR_MASK : 0) |
                       MM_STAT_DTB_MISS_MASK);
                 if (write) { write_misses++; } else { read_misses++; }
-                return (req->flags & VPTE) ? Pdtb_Miss_Fault : Ndtb_Miss_Fault;
+                return (req->flags & VPTE) ? (Fault *)PDtbMissFault : (Fault *)NDtbMissFault;
             }
 
             req->paddr = (pte->ppn << AlphaISA::PageShift) +
@@ -588,25 +588,25 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
                           MM_STAT_ACV_MASK |
                           (pte->fonw ? MM_STAT_FONW_MASK : 0));
                     write_acv++;
-                    return DTB_Fault_Fault;
+                    return DtbPageFault;
                 }
                 if (pte->fonw) {
                     fault(req, MM_STAT_WR_MASK |
                           MM_STAT_FONW_MASK);
                     write_acv++;
-                    return DTB_Fault_Fault;
+                    return DtbPageFault;
                 }
             } else {
                 if (!(pte->xre & MODE2MASK(mode))) {
                     fault(req, MM_STAT_ACV_MASK |
                           (pte->fonr ? MM_STAT_FONR_MASK : 0));
                     read_acv++;
-                    return DTB_Acv_Fault;
+                    return DtbAcvFault;
                 }
                 if (pte->fonr) {
                     fault(req, MM_STAT_FONR_MASK);
                     read_acv++;
-                    return DTB_Fault_Fault;
+                    return DtbPageFault;
                 }
             }
         }
@@ -619,11 +619,11 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
 
     // check that the physical address is ok (catch bad physical addresses)
     if (req->paddr & ~PAddrImplMask)
-        return Machine_Check_Fault;
+        return MachineCheckFault;
 
     checkCacheability(req);
 
-    return No_Fault;
+    return NoFault;
 }
 
 AlphaISA::PTE &
diff --git a/arch/alpha/alpha_memory.hh b/arch/alpha/alpha_memory.hh
index 788923434..849063f59 100644
--- a/arch/alpha/alpha_memory.hh
+++ b/arch/alpha/alpha_memory.hh
@@ -32,6 +32,7 @@
 #include <map>
 
 #include "arch/alpha/isa_traits.hh"
+#include "arch/alpha/faults.hh"
 #include "base/statistics.hh"
 #include "mem/mem_req.hh"
 #include "sim/sim_object.hh"
@@ -93,7 +94,7 @@ class AlphaITB : public AlphaTLB
     AlphaITB(const std::string &name, int size);
     virtual void regStats();
 
-    Fault translate(MemReqPtr &req) const;
+    Fault * translate(MemReqPtr &req) const;
 };
 
 class AlphaDTB : public AlphaTLB
@@ -119,7 +120,7 @@ class AlphaDTB : public AlphaTLB
     AlphaDTB(const std::string &name, int size);
     virtual void regStats();
 
-    Fault translate(MemReqPtr &req, bool write) const;
+    Fault * translate(MemReqPtr &req, bool write) const;
 };
 
 #endif // __ALPHA_MEMORY_HH__
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 125affd03..9d14be4d5 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -76,7 +76,7 @@ AlphaISA::initCPU(RegFile *regs)
     // CPU comes up with PAL regs enabled
     swap_palshadow(regs, true);
 
-    regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault];
+    regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr(ResetFault);
     regs->npc = regs->pc + sizeof(MachInst);
 }
 
@@ -84,25 +84,16 @@ AlphaISA::initCPU(RegFile *regs)
 //
 // alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
 //
-Addr
-AlphaISA::fault_addr[Num_Faults] = {
-    0x0000,	/* No_Fault */
-    0x0001,	/* Reset_Fault */
-    0x0401,	/* Machine_Check_Fault */
-    0x0501,	/* Arithmetic_Fault */
-    0x0101,	/* Interrupt_Fault */
-    0x0201,	/* Ndtb_Miss_Fault */
-    0x0281,	/* Pdtb_Miss_Fault */
-    0x0301,	/* Alignment_Fault */
-    0x0381,	/* DTB_Fault_Fault */
-    0x0381,	/* DTB_Acv_Fault */
-    0x0181,	/* ITB_Miss_Fault */
-    0x0181,	/* ITB_Fault_Fault */
-    0x0081,	/* ITB_Acv_Fault */
-    0x0481,	/* Unimplemented_Opcode_Fault */
-    0x0581,	/* Fen_Fault */
-    0x2001,	/* Pal_Fault */
-    0x0501,	/* Integer_Overflow_Fault: maps to Arithmetic_Fault */
+const Addr
+AlphaISA::fault_addr(Fault * fault)
+{
+        //Check for the system wide faults
+        if(fault == NoFault) return 0x0000;
+        else if(fault == MachineCheckFault) return 0x0401;
+        else if(fault == AlignmentFault) return 0x0301;
+        else if(fault == FakeMemFault) return 0x0000;
+        //Deal with the alpha specific faults
+        return ((AlphaFault*)fault)->vect;
 };
 
 const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
@@ -168,7 +159,7 @@ AlphaISA::processInterrupts(CPU *cpu)
     if (ipl && ipl > ipr[IPR_IPLR]) {
         ipr[IPR_ISR] = summary;
         ipr[IPR_INTID] = ipl;
-        cpu->trap(Interrupt_Fault);
+        cpu->trap(InterruptFault);
         DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
                 ipr[IPR_IPLR], ipl, summary);
     }
@@ -187,25 +178,25 @@ AlphaISA::zeroRegisters(CPU *cpu)
 }
 
 void
-ExecContext::ev5_trap(Fault fault)
+ExecContext::ev5_trap(Fault * fault)
 {
-    DPRINTF(Fault, "Fault %s at PC: %#x\n", FaultName(fault), regs.pc);
-    cpu->recordEvent(csprintf("Fault %s", FaultName(fault)));
+    DPRINTF(Fault, "Fault %s at PC: %#x\n", fault ? fault->name : "none", regs.pc);
+    cpu->recordEvent(csprintf("Fault %s", fault ? fault->name : "none"));
 
     assert(!misspeculating());
     kernelStats->fault(fault);
 
-    if (fault == Arithmetic_Fault)
+    if (fault == ArithmeticFault)
         panic("Arithmetic traps are unimplemented!");
 
     AlphaISA::InternalProcReg *ipr = regs.ipr;
 
     // exception restart address
-    if (fault != Interrupt_Fault || !inPalMode())
+    if (fault != InterruptFault || !inPalMode())
         ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
 
-    if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
-        fault == Interrupt_Fault && !inPalMode() */) {
+    if (fault == PalFault || fault == ArithmeticFault /* ||
+        fault == InterruptFault && !inPalMode() */) {
         // traps...  skip faulting instruction
         ipr[AlphaISA::IPR_EXC_ADDR] += 4;
     }
@@ -213,22 +204,22 @@ ExecContext::ev5_trap(Fault fault)
     if (!inPalMode())
         AlphaISA::swap_palshadow(&regs, true);
 
-    regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
+    regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr(fault);
     regs.npc = regs.pc + sizeof(MachInst);
 }
 
 
 void
-AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
+AlphaISA::intr_post(RegFile *regs, Fault * fault, Addr pc)
 {
     InternalProcReg *ipr = regs->ipr;
-    bool use_pc = (fault == No_Fault);
+    bool use_pc = (fault == NoFault);
 
-    if (fault == Arithmetic_Fault)
+    if (fault == ArithmeticFault)
         panic("arithmetic faults NYI...");
 
     // compute exception restart address
-    if (use_pc || fault == Pal_Fault || fault == Arithmetic_Fault) {
+    if (use_pc || fault == PalFault || fault == ArithmeticFault) {
         // traps...  skip faulting instruction
         ipr[IPR_EXC_ADDR] = regs->pc + 4;
     } else {
@@ -238,20 +229,20 @@ AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
 
     // jump to expection address (PAL PC bit set here as well...)
     if (!use_pc)
-        regs->npc = ipr[IPR_PAL_BASE] + fault_addr[fault];
+        regs->npc = ipr[IPR_PAL_BASE] + fault_addr(fault);
     else
         regs->npc = ipr[IPR_PAL_BASE] + pc;
 
     // that's it! (orders of magnitude less painful than x86)
 }
 
-Fault
+Fault *
 ExecContext::hwrei()
 {
     uint64_t *ipr = regs.ipr;
 
     if (!inPalMode())
-        return Unimplemented_Opcode_Fault;
+        return UnimplementedOpcodeFault;
 
     setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
 
@@ -265,11 +256,11 @@ ExecContext::hwrei()
     }
 
     // FIXME: XXX check for interrupts? XXX
-    return No_Fault;
+    return NoFault;
 }
 
 uint64_t
-ExecContext::readIpr(int idx, Fault &fault)
+ExecContext::readIpr(int idx, Fault * &fault)
 {
     uint64_t *ipr = regs.ipr;
     uint64_t retval = 0;	// return value, default 0
@@ -363,12 +354,12 @@ ExecContext::readIpr(int idx, Fault &fault)
       case AlphaISA::IPR_DTB_IAP:
       case AlphaISA::IPR_ITB_IA:
       case AlphaISA::IPR_ITB_IAP:
-        fault = Unimplemented_Opcode_Fault;
+        fault = UnimplementedOpcodeFault;
         break;
 
       default:
         // invalid IPR
-        fault = Unimplemented_Opcode_Fault;
+        fault = UnimplementedOpcodeFault;
         break;
     }
 
@@ -380,14 +371,14 @@ ExecContext::readIpr(int idx, Fault &fault)
 int break_ipl = -1;
 #endif
 
-Fault
+Fault *
 ExecContext::setIpr(int idx, uint64_t val)
 {
     uint64_t *ipr = regs.ipr;
     uint64_t old;
 
     if (misspeculating())
-        return No_Fault;
+        return NoFault;
 
     switch (idx) {
       case AlphaISA::IPR_PALtemp0:
@@ -533,7 +524,7 @@ ExecContext::setIpr(int idx, uint64_t val)
       case AlphaISA::IPR_ITB_PTE_TEMP:
       case AlphaISA::IPR_DTB_PTE_TEMP:
         // read-only registers
-        return Unimplemented_Opcode_Fault;
+        return UnimplementedOpcodeFault;
 
       case AlphaISA::IPR_HWINT_CLR:
       case AlphaISA::IPR_SL_XMIT:
@@ -635,11 +626,11 @@ ExecContext::setIpr(int idx, uint64_t val)
 
       default:
         // invalid IPR
-        return Unimplemented_Opcode_Fault;
+        return UnimplementedOpcodeFault;
     }
 
     // no error...
-    return No_Fault;
+    return NoFault;
 }
 
 /**
diff --git a/arch/alpha/faults.cc b/arch/alpha/faults.cc
index 3aecf029d..2dc3d9cbb 100644
--- a/arch/alpha/faults.cc
+++ b/arch/alpha/faults.cc
@@ -28,34 +28,40 @@
 
 #include "arch/alpha/faults.hh"
 
-namespace {
-    const char *
-    fault_name[Num_Faults] = {
-        "none",
-        "reset",
-        "mchk",
-        "arith",
-        "interrupt",
-        "dtb_miss_single",
-        "dtb_miss_double",
-        "unalign",
-        "dfault",
-        "dfault",
-        "itbmiss",
-        "itbmiss",
-        "iaccvio",
-        "opdec",
-        "fen",
-        "pal",
-    };
-}
+ResetFaultType * ResetFault = new ResetFaultType("reset", 1, 0x0001);
+ArithmeticFaultType * ArithmeticFault = new ArithmeticFaultType("arith", 3, 0x0501);
+InterruptFaultType * InterruptFault = new InterruptFaultType("interrupt", 4, 0x0101);
+NDtbMissFaultType * NDtbMissFault = new NDtbMissFaultType("dtb_miss_single", 5, 0x0201);
+PDtbMissFaultType * PDtbMissFault = new PDtbMissFaultType("dtb_miss_double", 6, 0x0281);
+DtbPageFaultType * DtbPageFault = new DtbPageFaultType("dfault", 8, 0x0381);
+DtbAcvFaultType * DtbAcvFault = new DtbAcvFaultType("dfault", 9, 0x0381);
+ItbMissFaultType * ItbMissFault = new ItbMissFaultType("itbmiss", 10, 0x0181);
+ItbPageFaultType * ItbPageFault = new ItbPageFaultType("itbmiss", 11, 0x0181);
+ItbAcvFaultType * ItbAcvFault = new ItbAcvFaultType("iaccvio", 12, 0x0081);
+UnimplementedOpcodeFaultType * UnimplementedOpcodeFault = new UnimplementedOpcodeFaultType("opdec", 13, 0x0481);
+FloatEnableFaultType * FloatEnableFault = new FloatEnableFaultType("fen", 14, 0x0581);
+PalFaultType * PalFault = new PalFaultType("pal", 15, 0x2001);
+IntegerOverflowFaultType * IntegerOverflowFault = new IntegerOverflowFaultType("intover", 16, 0x0501);
 
-const char *
-FaultName(int index)
-{
-    if (index < 0 || index >= Num_Faults)
-        return 0;
-
-    return fault_name[index];
-}
+Fault ** ListOfFaults[] = {
+        (Fault **)&NoFault,
+        (Fault **)&ResetFault,
+        (Fault **)&MachineCheckFault,
+        (Fault **)&ArithmeticFault,
+        (Fault **)&InterruptFault,
+        (Fault **)&NDtbMissFault,
+        (Fault **)&PDtbMissFault,
+        (Fault **)&AlignmentFault,
+        (Fault **)&DtbPageFault,
+        (Fault **)&DtbAcvFault,
+        (Fault **)&ItbMissFault,
+        (Fault **)&ItbPageFault,
+        (Fault **)&ItbAcvFault,
+        (Fault **)&UnimplementedOpcodeFault,
+        (Fault **)&FloatEnableFault,
+        (Fault **)&PalFault,
+        (Fault **)&IntegerOverflowFault,
+        (Fault **)&FakeMemFault
+        };
 
+int NumFaults = sizeof(ListOfFaults) / sizeof(Fault **);
diff --git a/arch/alpha/faults.hh b/arch/alpha/faults.hh
index bbac7cbf2..2bb929a1e 100644
--- a/arch/alpha/faults.hh
+++ b/arch/alpha/faults.hh
@@ -26,32 +26,104 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __FAULTS_HH__
-#define __FAULTS_HH__
-
-enum Fault {
-    No_Fault,
-    Reset_Fault,		// processor reset
-    Machine_Check_Fault,	// machine check (also internal S/W fault)
-    Arithmetic_Fault,		// FP exception
-    Interrupt_Fault,		// external interrupt
-    Ndtb_Miss_Fault,		// DTB miss
-    Pdtb_Miss_Fault,		// nested DTB miss
-    Alignment_Fault,		// unaligned access
-    DTB_Fault_Fault,		// DTB page fault
-    DTB_Acv_Fault,		// DTB access violation
-    ITB_Miss_Fault,		// ITB miss
-    ITB_Fault_Fault,		// ITB page fault
-    ITB_Acv_Fault,		// ITB access violation
-    Unimplemented_Opcode_Fault,	// invalid/unimplemented instruction
-    Fen_Fault,			// FP not-enabled fault
-    Pal_Fault,			// call_pal S/W interrupt
-    Integer_Overflow_Fault,
-    Fake_Mem_Fault,
-    Num_Faults			// number of faults
+#ifndef __ALPHA_FAULTS_HH__
+#define __ALPHA_FAULTS_HH__
+
+#include "sim/faults.hh"
+#include "arch/isa_traits.hh" //For the Addr type
+
+class AlphaFault : public Fault
+{
+public:
+        AlphaFault(char * newName, int newId, Addr newVect) : Fault(newName, newId), vect(newVect) {;}
+        TheISA::Addr vect;
 };
 
-const char *
-FaultName(int index);
+extern class ResetFaultType : public AlphaFault
+{
+public:
+        ResetFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
+} * ResetFault;
+
+extern class ArithmeticFaultType : public AlphaFault
+{
+public:
+        ArithmeticFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
+} * ArithmeticFault;
+
+extern class InterruptFaultType : public AlphaFault
+{
+public:
+        InterruptFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
+} * InterruptFault;
+
+extern class NDtbMissFaultType : public AlphaFault
+{
+public:
+        NDtbMissFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
+} * NDtbMissFault;
+
+extern class PDtbMissFaultType : public AlphaFault
+{
+public:
+        PDtbMissFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
+} * PDtbMissFault;
+
+extern class DtbPageFaultType : public AlphaFault
+{
+public:
+        DtbPageFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
+} * DtbPageFault;
+
+extern class DtbAcvFaultType : public AlphaFault
+{
+public:
+        DtbAcvFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
+} * DtbAcvFault;
+
+extern class ItbMissFaultType : public AlphaFault
+{
+public:
+        ItbMissFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
+} * ItbMissFault;
+
+extern class ItbPageFaultType : public AlphaFault
+{
+public:
+        ItbPageFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
+} * ItbPageFault;
+
+extern class ItbAcvFaultType : public AlphaFault
+{
+public:
+        ItbAcvFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
+} * ItbAcvFault;
+
+extern class UnimplementedOpcodeFaultType : public AlphaFault
+{
+public:
+        UnimplementedOpcodeFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
+} * UnimplementedOpcodeFault;
+
+extern class FloatEnableFaultType : public AlphaFault
+{
+public:
+        FloatEnableFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
+} * FloatEnableFault;
+
+extern class PalFaultType : public AlphaFault
+{
+public:
+        PalFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
+} * PalFault;
+
+extern class IntegerOverflowFaultType : public AlphaFault
+{
+public:
+        IntegerOverflowFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
+} * IntegerOverflowFault;
+
+extern Fault ** ListOfFaults[];
+extern int NumFaults;
 
 #endif // __FAULTS_HH__
diff --git a/arch/alpha/isa/decoder.isa b/arch/alpha/isa/decoder.isa
index aff8571e9..37b15416b 100644
--- a/arch/alpha/isa/decoder.isa
+++ b/arch/alpha/isa/decoder.isa
@@ -98,7 +98,7 @@ decode OPCODE default Unknown::unknown() {
                 // signed overflow occurs when operands have same sign
                 // and sign of result does not match.
                 if (Ra.sl<31:> == Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
-                    fault = Integer_Overflow_Fault;
+                    fault = IntegerOverflowFault;
                 Rc.sl = tmp;
             }});
             0x02: s4addl({{ Rc.sl = (Ra.sl << 2) + Rb_or_imm.sl; }});
@@ -110,7 +110,7 @@ decode OPCODE default Unknown::unknown() {
                 // signed overflow occurs when operands have same sign
                 // and sign of result does not match.
                 if (Ra<63:> == Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
-                    fault = Integer_Overflow_Fault;
+                    fault = IntegerOverflowFault;
                 Rc = tmp;
             }});
             0x22: s4addq({{ Rc = (Ra << 2) + Rb_or_imm; }});
@@ -124,7 +124,7 @@ decode OPCODE default Unknown::unknown() {
                 // sign bit of the subtrahend (Rb), i.e., if the initial
                 // signs are the *same* then no overflow can occur
                 if (Ra.sl<31:> != Rb_or_imm.sl<31:> && tmp<31:> != Ra.sl<31:>)
-                    fault = Integer_Overflow_Fault;
+                    fault = IntegerOverflowFault;
                 Rc.sl = tmp;
             }});
             0x0b: s4subl({{ Rc.sl = (Ra.sl << 2) - Rb_or_imm.sl; }});
@@ -138,7 +138,7 @@ decode OPCODE default Unknown::unknown() {
                 // sign bit of the subtrahend (Rb), i.e., if the initial
                 // signs are the *same* then no overflow can occur
                 if (Ra<63:> != Rb_or_imm<63:> && tmp<63:> != Ra<63:>)
-                    fault = Integer_Overflow_Fault;
+                    fault = IntegerOverflowFault;
                 Rc = tmp;
             }});
             0x2b: s4subq({{ Rc = (Ra << 2) - Rb_or_imm; }});
@@ -299,7 +299,7 @@ decode OPCODE default Unknown::unknown() {
                 // checking the upper 33 bits for all 0s or all 1s.
                 uint64_t sign_bits = tmp<63:31>;
                 if (sign_bits != 0 && sign_bits != mask(33))
-                    fault = Integer_Overflow_Fault;
+                    fault = IntegerOverflowFault;
                 Rc.sl = tmp<31:0>;
             }}, IntMultOp);
             0x60: mulqv({{
@@ -310,7 +310,7 @@ decode OPCODE default Unknown::unknown() {
                 // the lower 64
                 if (!((hi == 0 && lo<63:> == 0) ||
                       (hi == mask(64) && lo<63:> == 1)))
-                    fault = Integer_Overflow_Fault;
+                    fault = IntegerOverflowFault;
                 Rc = lo;
             }}, IntMultOp);
         }
@@ -427,19 +427,19 @@ decode OPCODE default Unknown::unknown() {
 #if SS_COMPATIBLE_FP
                     0x0b: sqrts({{
                         if (Fb < 0.0)
-                            fault = Arithmetic_Fault;
+                            fault = ArithmeticFault;
                         Fc = sqrt(Fb);
                     }}, FloatSqrtOp);
 #else
                     0x0b: sqrts({{
                         if (Fb.sf < 0.0)
-                            fault = Arithmetic_Fault;
+                            fault = ArithmeticFault;
                         Fc.sf = sqrt(Fb.sf);
                     }}, FloatSqrtOp);
 #endif
                     0x2b: sqrtt({{
                         if (Fb < 0.0)
-                            fault = Arithmetic_Fault;
+                            fault = ArithmeticFault;
                         Fc = sqrt(Fb);
                     }}, FloatSqrtOp);
                 }
@@ -570,7 +570,7 @@ decode OPCODE default Unknown::unknown() {
                 // checking the upper 33 bits for all 0s or all 1s.
                 uint64_t sign_bits = Fb.uq<63:31>;
                 if (sign_bits != 0 && sign_bits != mask(33))
-                    fault = Integer_Overflow_Fault;
+                    fault = IntegerOverflowFault;
                 Fc.uq = (Fb.uq<31:30> << 62) | (Fb.uq<29:0> << 29);
             }});
 
@@ -673,7 +673,7 @@ decode OPCODE default Unknown::unknown() {
              && xc->readIpr(AlphaISA::IPR_ICM, fault) != AlphaISA::mode_kernel)) {
             // invalid pal function code, or attempt to do privileged
             // PAL call in non-kernel mode
-            fault = Unimplemented_Opcode_Fault;
+            fault = UnimplementedOpcodeFault;
         }
         else {
             // check to see if simulator wants to do something special
@@ -729,7 +729,7 @@ decode OPCODE default Unknown::unknown() {
         0x19: hw_mfpr({{
             // this instruction is only valid in PAL mode
             if (!xc->inPalMode()) {
-                fault = Unimplemented_Opcode_Fault;
+                fault = UnimplementedOpcodeFault;
             }
             else {
                 Ra = xc->readIpr(ipr_index, fault);
@@ -738,7 +738,7 @@ decode OPCODE default Unknown::unknown() {
         0x1d: hw_mtpr({{
             // this instruction is only valid in PAL mode
             if (!xc->inPalMode()) {
-                fault = Unimplemented_Opcode_Fault;
+                fault = UnimplementedOpcodeFault;
             }
             else {
                 xc->setIpr(ipr_index, Ra);
diff --git a/arch/alpha/isa/fp.isa b/arch/alpha/isa/fp.isa
index 0abc814be..c718c5524 100644
--- a/arch/alpha/isa/fp.isa
+++ b/arch/alpha/isa/fp.isa
@@ -29,21 +29,21 @@
 output exec {{
     /// Check "FP enabled" machine status bit.  Called when executing any FP
     /// instruction in full-system mode.
-    /// @retval Full-system mode: No_Fault if FP is enabled, Fen_Fault
-    /// if not.  Non-full-system mode: always returns No_Fault.
+    /// @retval Full-system mode: NoFault if FP is enabled, FenFault
+    /// if not.  Non-full-system mode: always returns NoFault.
 #if FULL_SYSTEM
-    inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
+    inline Fault * checkFpEnableFault(%(CPU_exec_context)s *xc)
     {
-        Fault fault = No_Fault;	// dummy... this ipr access should not fault
+        Fault * fault = NoFault;	// dummy... this ipr access should not fault
         if (!EV5::ICSR_FPE(xc->readIpr(AlphaISA::IPR_ICSR, fault))) {
-            fault = Fen_Fault;
+            fault = FloatEnableFault;
         }
         return fault;
     }
 #else
-    inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
+    inline Fault * checkFpEnableFault(%(CPU_exec_context)s *xc)
     {
-        return No_Fault;
+        return NoFault;
     }
 #endif
 }};
@@ -199,7 +199,7 @@ output decoder {{
 // FP instruction class execute method template.  Handles non-standard
 // rounding modes.
 def template FloatingPointExecute {{
-    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+    Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
     {
         if (trappingMode != Imprecise && !warnedOnTrapping) {
@@ -208,7 +208,7 @@ def template FloatingPointExecute {{
             warnedOnTrapping = true;
         }
 
-        Fault fault = No_Fault;
+        Fault * fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_decl)s;
@@ -230,7 +230,7 @@ def template FloatingPointExecute {{
         %(code)s;
 #endif
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(op_wb)s;
         }
 
@@ -242,7 +242,7 @@ def template FloatingPointExecute {{
 // rounding mode control is needed.  Like BasicExecute, but includes
 // check & warning for non-standard trapping mode.
 def template FPFixedRoundingExecute {{
-    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+    Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
     {
         if (trappingMode != Imprecise && !warnedOnTrapping) {
@@ -251,14 +251,14 @@ def template FPFixedRoundingExecute {{
             warnedOnTrapping = true;
         }
 
-        Fault fault = No_Fault;
+        Fault * fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_decl)s;
         %(op_rd)s;
         %(code)s;
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(op_wb)s;
         }
 
diff --git a/arch/alpha/isa/main.isa b/arch/alpha/isa/main.isa
index a2860f17b..baf2f2658 100644
--- a/arch/alpha/isa/main.isa
+++ b/arch/alpha/isa/main.isa
@@ -33,6 +33,7 @@ output header {{
 
 #include "config/ss_compatible_fp.hh"
 #include "cpu/static_inst.hh"
+#include "arch/alpha/faults.hh"
 #include "mem/mem_req.hh"  // some constructors use MemReq flags
 }};
 
@@ -253,7 +254,7 @@ output decoder {{
 
 // Declarations for execute() methods.
 def template BasicExecDeclare {{
-    Fault execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
+    Fault * execute(%(CPU_exec_context)s *, Trace::InstRecord *) const;
 }};
 
 // Basic instruction class declaration template.
@@ -282,17 +283,17 @@ def template BasicConstructor {{
 
 // Basic instruction class execute method template.
 def template BasicExecute {{
-    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+    Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
     {
-        Fault fault = No_Fault;
+        Fault * fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_decl)s;
         %(op_rd)s;
         %(code)s;
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(op_wb)s;
         }
 
@@ -377,10 +378,10 @@ output decoder {{
 }};
 
 output exec {{
-    Fault
+    Fault *
     Nop::execute(%(CPU_exec_context)s *, Trace::InstRecord *) const
     {
-        return No_Fault;
+        return NoFault;
     }
 }};
 
diff --git a/arch/alpha/isa/mem.isa b/arch/alpha/isa/mem.isa
index 45afd378c..1f6907181 100644
--- a/arch/alpha/isa/mem.isa
+++ b/arch/alpha/isa/mem.isa
@@ -193,19 +193,19 @@ def template LoadStoreConstructor {{
 
 
 def template EACompExecute {{
-    Fault
+    Fault *
     %(class_name)s::EAComp::execute(%(CPU_exec_context)s *xc,
                                    Trace::InstRecord *traceData) const
     {
         Addr EA;
-        Fault fault = No_Fault;
+        Fault * fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_decl)s;
         %(op_rd)s;
         %(code)s;
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(op_wb)s;
             xc->setEA(EA);
         }
@@ -215,24 +215,24 @@ def template EACompExecute {{
 }};
 
 def template LoadMemAccExecute {{
-    Fault
+    Fault *
     %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
                                    Trace::InstRecord *traceData) const
     {
         Addr EA;
-        Fault fault = No_Fault;
+        Fault * fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_decl)s;
         %(op_rd)s;
         EA = xc->getEA();
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
             %(code)s;
         }
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(op_wb)s;
         }
 
@@ -242,23 +242,23 @@ def template LoadMemAccExecute {{
 
 
 def template LoadExecute {{
-    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+    Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
     {
         Addr EA;
-        Fault fault = No_Fault;
+        Fault * fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_decl)s;
         %(op_rd)s;
         %(ea_code)s;
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             fault = xc->read(EA, (uint%(mem_acc_size)d_t&)Mem, memAccessFlags);
             %(memacc_code)s;
         }
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(op_wb)s;
         }
 
@@ -268,12 +268,12 @@ def template LoadExecute {{
 
 
 def template StoreMemAccExecute {{
-    Fault
+    Fault *
     %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
                                    Trace::InstRecord *traceData) const
     {
         Addr EA;
-        Fault fault = No_Fault;
+        Fault * fault = NoFault;
         uint64_t write_result = 0;
 
         %(fp_enable_check)s;
@@ -281,21 +281,21 @@ def template StoreMemAccExecute {{
         %(op_rd)s;
         EA = xc->getEA();
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(code)s;
         }
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
                               memAccessFlags, &write_result);
             if (traceData) { traceData->setData(Mem); }
         }
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(postacc_code)s;
         }
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(op_wb)s;
         }
 
@@ -305,11 +305,11 @@ def template StoreMemAccExecute {{
 
 
 def template StoreExecute {{
-    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+    Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
     {
         Addr EA;
-        Fault fault = No_Fault;
+        Fault * fault = NoFault;
         uint64_t write_result = 0;
 
         %(fp_enable_check)s;
@@ -317,21 +317,21 @@ def template StoreExecute {{
         %(op_rd)s;
         %(ea_code)s;
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(memacc_code)s;
         }
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             fault = xc->write((uint%(mem_acc_size)d_t&)Mem, EA,
                               memAccessFlags, &write_result);
             if (traceData) { traceData->setData(Mem); }
         }
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(postacc_code)s;
         }
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(op_wb)s;
         }
 
@@ -341,42 +341,42 @@ def template StoreExecute {{
 
 
 def template MiscMemAccExecute {{
-    Fault %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
+    Fault * %(class_name)s::MemAcc::execute(%(CPU_exec_context)s *xc,
                                           Trace::InstRecord *traceData) const
     {
         Addr EA;
-        Fault fault = No_Fault;
+        Fault * fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_decl)s;
         %(op_rd)s;
         EA = xc->getEA();
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(code)s;
         }
 
-        return No_Fault;
+        return NoFault;
     }
 }};
 
 def template MiscExecute {{
-    Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+    Fault * %(class_name)s::execute(%(CPU_exec_context)s *xc,
                                   Trace::InstRecord *traceData) const
     {
         Addr EA;
-        Fault fault = No_Fault;
+        Fault * fault = NoFault;
 
         %(fp_enable_check)s;
         %(op_decl)s;
         %(op_rd)s;
         %(ea_code)s;
 
-        if (fault == No_Fault) {
+        if (fault == NoFault) {
             %(memacc_code)s;
         }
 
-        return No_Fault;
+        return NoFault;
     }
 }};
 
diff --git a/arch/alpha/isa/unimp.isa b/arch/alpha/isa/unimp.isa
index 767888157..ce8197708 100644
--- a/arch/alpha/isa/unimp.isa
+++ b/arch/alpha/isa/unimp.isa
@@ -105,16 +105,16 @@ output decoder {{
 }};
 
 output exec {{
-    Fault
+    Fault *
     FailUnimplemented::execute(%(CPU_exec_context)s *xc,
                                Trace::InstRecord *traceData) const
     {
         panic("attempt to execute unimplemented instruction '%s' "
               "(inst 0x%08x, opcode 0x%x)", mnemonic, machInst, OPCODE);
-        return Unimplemented_Opcode_Fault;
+        return UnimplementedOpcodeFault;
     }
 
-    Fault
+    Fault *
     WarnUnimplemented::execute(%(CPU_exec_context)s *xc,
                                Trace::InstRecord *traceData) const
     {
@@ -123,7 +123,7 @@ output exec {{
             warned = true;
         }
 
-        return No_Fault;
+        return NoFault;
     }
 }};
 
diff --git a/arch/alpha/isa/unknown.isa b/arch/alpha/isa/unknown.isa
index 6eba5b4f9..e7f8bc8db 100644
--- a/arch/alpha/isa/unknown.isa
+++ b/arch/alpha/isa/unknown.isa
@@ -36,13 +36,13 @@ output decoder {{
 }};
 
 output exec {{
-    Fault
+    Fault *
     Unknown::execute(%(CPU_exec_context)s *xc,
                      Trace::InstRecord *traceData) const
     {
         panic("attempt to execute unknown instruction "
               "(inst 0x%08x, opcode 0x%x)", machInst, OPCODE);
-        return Unimplemented_Opcode_Fault;
+        return UnimplementedOpcodeFault;
     }
 }};
 
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index a17cde49b..a6e34acbb 100644
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -32,10 +32,11 @@
 namespace LittleEndianGuest {}
 using namespace LittleEndianGuest;
 
-#include "arch/alpha/faults.hh"
+//#include "arch/alpha/faults.hh"
 #include "base/misc.hh"
 #include "config/full_system.hh"
 #include "sim/host.hh"
+#include "sim/faults.hh"
 
 class FastCPU;
 class FullCPU;