Merge ktlim@zizzer:/bk/m5

into  zamp.eecs.umich.edu:/z/ktlim2/m5-proxyxc

Further changes still need to be made to the XC code.

arch/alpha/ev5.cc:
arch/alpha/freebsd/system.cc:
arch/alpha/linux/system.cc:
base/remote_gdb.cc:
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
kern/kernel_stats.cc:
sim/pseudo_inst.cc:
    Hand merge.

--HG--
rename : kern/freebsd/freebsd_system.cc => arch/alpha/freebsd/system.cc
rename : kern/linux/linux_system.cc => arch/alpha/linux/system.cc
rename : kern/linux/linux_threadinfo.hh => arch/alpha/linux/threadinfo.hh
rename : arch/alpha/alpha_linux_process.cc => arch/alpha/linux_process.cc
rename : arch/alpha/alpha_memory.cc => arch/alpha/tlb.cc
rename : arch/alpha/alpha_tru64_process.cc => arch/alpha/tru64_process.cc
rename : cpu/exec_context.cc => cpu/cpu_exec_context.cc
rename : cpu/exec_context.hh => cpu/cpu_exec_context.hh
extra : convert_revision : c1fe71fdd87d1fcd376f4feec69fc3fa29152e3e

12 files changed, 91 insertions, 91 deletions

diff --git a/arch/alpha/arguments.cc b/arch/alpha/arguments.cc
index 4e8190cbc..019390aeb 100644
--- a/arch/alpha/arguments.cc
+++ b/arch/alpha/arguments.cc
@@ -54,13 +54,13 @@ AlphaArguments::getArg(bool fp)
 {
     if (number < 6) {
         if (fp)
-            return xc->regs.floatRegFile.q[16 + number];
+            return xc->readFloatRegInt(16 + number);
         else
-            return xc->regs.intRegFile[16 + number];
+            return xc->readIntReg(16 + number);
     } else {
-        Addr sp = xc->regs.intRegFile[30];
+        Addr sp = xc->readIntReg(30);
         Addr paddr = vtophys(xc, sp + (number-6) * sizeof(uint64_t));
-        return xc->physmem->phys_read_qword(paddr);
+        return xc->getPhysMemPtr()->phys_read_qword(paddr);
     }
 }
 
diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index e313c1a1c..11faf1850 100644
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -34,6 +34,7 @@
 #include "base/stats/events.hh"
 #include "config/full_system.hh"
 #include "cpu/base.hh"
+#include "cpu/cpu_exec_context.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/fast/cpu.hh"
 #include "kern/kernel_stats.hh"
@@ -49,15 +50,15 @@ using namespace EV5;
 //  Machine dependent functions
 //
 void
-AlphaISA::initCPU(RegFile *regs, int cpuId)
+AlphaISA::initCPU(ExecContext *xc, int cpuId)
 {
-    initIPRs(&regs->miscRegs, cpuId);
+    initIPRs(xc, cpuId);
 
-    regs->intRegFile[16] = cpuId;
-    regs->intRegFile[0] = cpuId;
+    xc->setIntReg(16, cpuId);
+    xc->setIntReg(0, cpuId);
 
-    regs->pc = regs->miscRegs.readReg(IPR_PAL_BASE) + (new ResetFault)->vect();
-    regs->npc = regs->pc + sizeof(MachInst);
+    xc->setPC(xc->readMiscReg(IPR_PAL_BASE) + (new ResetFault)->vect());
+    xc->setNextPC(xc->readPC() + sizeof(MachInst));
 }
 
 ////////////////////////////////////////////////////////////////////////
@@ -65,13 +66,15 @@ AlphaISA::initCPU(RegFile *regs, int cpuId)
 //
 //
 void
-AlphaISA::initIPRs(MiscRegFile *miscRegs, int cpuId)
+AlphaISA::initIPRs(ExecContext *xc, int cpuId)
 {
-    miscRegs->clearIprs();
+    for (int i = 0; i < NumInternalProcRegs; ++i) {
+        xc->setMiscReg(i, 0);
+    }
 
-    miscRegs->setReg(IPR_PAL_BASE, PalBase);
-    miscRegs->setReg(IPR_MCSR, 0x6);
-    miscRegs->setReg(IPR_PALtemp16, cpuId);
+    xc->setMiscReg(IPR_PAL_BASE, PalBase);
+    xc->setMiscReg(IPR_MCSR, 0x6);
+    xc->setMiscReg(IPR_PALtemp16, cpuId);
 }
 
 
@@ -130,12 +133,12 @@ AlphaISA::zeroRegisters(CPU *cpu)
     // Insure ISA semantics
     // (no longer very clean due to the change in setIntReg() in the
     // cpu model.  Consider changing later.)
-    cpu->xc->setIntReg(ZeroReg, 0);
-    cpu->xc->setFloatRegDouble(ZeroReg, 0.0);
+    cpu->cpuXC->setIntReg(ZeroReg, 0);
+    cpu->cpuXC->setFloatRegDouble(ZeroReg, 0.0);
 }
 
 Fault
-ExecContext::hwrei()
+CPUExecContext::hwrei()
 {
     if (!inPalMode())
         return new UnimplementedOpcodeFault;
@@ -143,7 +146,7 @@ ExecContext::hwrei()
     setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
 
     if (!misspeculating()) {
-        kernelStats->hwrei();
+        cpu->kernelStats->hwrei();
 
         cpu->checkInterrupts = true;
     }
@@ -152,12 +155,6 @@ ExecContext::hwrei()
     return NoFault;
 }
 
-void
-AlphaISA::MiscRegFile::clearIprs()
-{
-    bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
-}
-
 AlphaISA::MiscReg
 AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc)
 {
@@ -213,7 +210,7 @@ AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc)
 
       case AlphaISA::IPR_CC:
         retval |= ipr[idx] & ULL(0xffffffff00000000);
-        retval |= xc->cpu->curCycle()  & ULL(0x00000000ffffffff);
+        retval |= xc->getCpuPtr()->curCycle()  & ULL(0x00000000ffffffff);
         break;
 
       case AlphaISA::IPR_VA:
@@ -230,7 +227,7 @@ AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ExecContext *xc)
 
       case AlphaISA::IPR_DTB_PTE:
         {
-            AlphaISA::PTE &pte = xc->dtb->index(!xc->misspeculating());
+            AlphaISA::PTE &pte = xc->getDTBPtr()->index(!xc->misspeculating());
 
             retval |= ((u_int64_t)pte.ppn & ULL(0x7ffffff)) << 32;
             retval |= ((u_int64_t)pte.xre & ULL(0xf)) << 8;
@@ -327,7 +324,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
         // write entire quad w/ no side-effect
         old = ipr[idx];
         ipr[idx] = val;
-        xc->kernelStats->context(old, val);
+        xc->getCpuPtr()->kernelStats->context(old, val, xc);
         break;
 
       case AlphaISA::IPR_DTB_PTE:
@@ -354,14 +351,14 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
 
         // only write least significant five bits - interrupt level
         ipr[idx] = val & 0x1f;
-        xc->kernelStats->swpipl(ipr[idx]);
+        xc->getCpuPtr()->kernelStats->swpipl(ipr[idx]);
         break;
 
       case AlphaISA::IPR_DTB_CM:
         if (val & 0x18)
-            xc->kernelStats->mode(Kernel::user);
+            xc->getCpuPtr()->kernelStats->mode(Kernel::user, xc);
         else
-            xc->kernelStats->mode(Kernel::kernel);
+            xc->getCpuPtr()->kernelStats->mode(Kernel::kernel, xc);
 
       case AlphaISA::IPR_ICM:
         // only write two mode bits - processor mode
@@ -435,21 +432,22 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
         // really a control write
         ipr[idx] = 0;
 
-        xc->dtb->flushAll();
+        xc->getDTBPtr()->flushAll();
         break;
 
       case AlphaISA::IPR_DTB_IAP:
         // really a control write
         ipr[idx] = 0;
 
-        xc->dtb->flushProcesses();
+        xc->getDTBPtr()->flushProcesses();
         break;
 
       case AlphaISA::IPR_DTB_IS:
         // really a control write
         ipr[idx] = val;
 
-        xc->dtb->flushAddr(val, DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
+        xc->getDTBPtr()->flushAddr(val,
+                                   DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
         break;
 
       case AlphaISA::IPR_DTB_TAG: {
@@ -472,7 +470,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
           pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
 
           // insert new TAG/PTE value into data TLB
-          xc->dtb->insert(val, pte);
+          xc->getDTBPtr()->insert(val, pte);
       }
         break;
 
@@ -496,7 +494,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
           pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
 
           // insert new TAG/PTE value into data TLB
-          xc->itb->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
+          xc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
       }
         break;
 
@@ -504,21 +502,22 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
         // really a control write
         ipr[idx] = 0;
 
-        xc->itb->flushAll();
+        xc->getITBPtr()->flushAll();
         break;
 
       case AlphaISA::IPR_ITB_IAP:
         // really a control write
         ipr[idx] = 0;
 
-        xc->itb->flushProcesses();
+        xc->getITBPtr()->flushProcesses();
         break;
 
       case AlphaISA::IPR_ITB_IS:
         // really a control write
         ipr[idx] = val;
 
-        xc->itb->flushAddr(val, ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
+        xc->getITBPtr()->flushAddr(val,
+                                   ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
         break;
 
       default:
@@ -535,9 +534,9 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc)
  * If return value is false, actual PAL call will be suppressed.
  */
 bool
-ExecContext::simPalCheck(int palFunc)
+CPUExecContext::simPalCheck(int palFunc)
 {
-    kernelStats->callpal(palFunc);
+    cpu->kernelStats->callpal(palFunc, proxy);
 
     switch (palFunc) {
       case PAL::halt:
diff --git a/arch/alpha/freebsd/system.cc b/arch/alpha/freebsd/system.cc
index 681d4ad46..e32053afd 100644
--- a/arch/alpha/freebsd/system.cc
+++ b/arch/alpha/freebsd/system.cc
@@ -39,8 +39,8 @@
 #include "cpu/exec_context.hh"
 #include "mem/functional/memory_control.hh"
 #include "mem/functional/physical.hh"
-#include "sim/builder.hh"
 #include "arch/isa_traits.hh"
+#include "sim/builder.hh"
 #include "sim/byteswap.hh"
 #include "arch/vtophys.hh"
 
@@ -77,8 +77,8 @@ FreebsdAlphaSystem::doCalibrateClocks(ExecContext *xc)
     Addr ppc_paddr = 0;
     Addr timer_paddr = 0;
 
-    ppc_vaddr = (Addr)xc->regs.intRegFile[ArgumentReg1];
-    timer_vaddr = (Addr)xc->regs.intRegFile[ArgumentReg2];
+    ppc_vaddr = (Addr)xc->readIntReg(ArgumentReg1);
+    timer_vaddr = (Addr)xc->readIntReg(ArgumentReg2);
 
     ppc_paddr = vtophys(physmem, ppc_vaddr);
     timer_paddr = vtophys(physmem, timer_vaddr);
@@ -95,7 +95,7 @@ void
 FreebsdAlphaSystem::SkipCalibrateClocksEvent::process(ExecContext *xc)
 {
     SkipFuncEvent::process(xc);
-    ((FreebsdAlphaSystem *)xc->system)->doCalibrateClocks(xc);
+    ((FreebsdAlphaSystem *)xc->getSystemPtr())->doCalibrateClocks(xc);
 }
 
 
diff --git a/arch/alpha/isa/decoder.isa b/arch/alpha/isa/decoder.isa
index 54bc97920..e09673269 100644
--- a/arch/alpha/isa/decoder.isa
+++ b/arch/alpha/isa/decoder.isa
@@ -784,7 +784,7 @@ decode OPCODE default Unknown::unknown() {
             0x21: m5exit({{
                 AlphaPseudo::m5exit(xc->xcBase(), R16);
             }}, No_OpClass, IsNonSpeculative);
-            0x30: initparam({{ Ra = xc->xcBase()->cpu->system->init_param; }});
+            0x30: initparam({{ Ra = xc->xcBase()->getCpuPtr()->system->init_param; }});
             0x40: resetstats({{
                 AlphaPseudo::resetstats(xc->xcBase(), R16, R17);
             }}, IsNonSpeculative);
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index a551db485..b4084723f 100644
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -174,8 +174,6 @@ extern const int reg_redir[NumIntRegs];
                                ExecContext *xc);
 
 #if FULL_SYSTEM
-        void clearIprs();
-
       protected:
         InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
 
diff --git a/arch/alpha/linux/system.cc b/arch/alpha/linux/system.cc
index 6a820d14f..f9275d15e 100644
--- a/arch/alpha/linux/system.cc
+++ b/arch/alpha/linux/system.cc
@@ -195,7 +195,7 @@ LinuxAlphaSystem::setDelayLoop(ExecContext *xc)
         uint8_t *loops_per_jiffy =
             physmem->dma_addr(paddr, sizeof(uint32_t));
 
-        Tick cpuFreq = xc->cpu->frequency();
+        Tick cpuFreq = xc->getCpuPtr()->frequency();
         Tick intrFreq = platform->intrFrequency();
         *(uint32_t *)loops_per_jiffy =
             (uint32_t)((cpuFreq / intrFreq) * 0.9988);
@@ -208,7 +208,7 @@ LinuxAlphaSystem::SkipDelayLoopEvent::process(ExecContext *xc)
 {
     SkipFuncEvent::process(xc);
     // calculate and set loops_per_jiffy
-    ((LinuxAlphaSystem *)xc->system)->setDelayLoop(xc);
+    ((LinuxAlphaSystem *)xc->getSystemPtr())->setDelayLoop(xc);
 }
 
 void
diff --git a/arch/alpha/linux/threadinfo.hh b/arch/alpha/linux/threadinfo.hh
index bdb8e1e4c..8f03c9314 100644
--- a/arch/alpha/linux/threadinfo.hh
+++ b/arch/alpha/linux/threadinfo.hh
@@ -54,7 +54,7 @@ class ThreadInfo
          * thread_info struct. So we can get the address by masking off
          * the lower 14 bits.
          */
-        current = xc->regs.intRegFile[TheISA::StackPointerReg] & ~0x3fff;
+        current = xc->readIntReg(TheISA::StackPointerReg) & ~0x3fff;
         return VPtr<thread_info>(xc, current);
     }
 
diff --git a/arch/alpha/linux_process.cc b/arch/alpha/linux_process.cc
index 0b193fb55..b80966133 100644
--- a/arch/alpha/linux_process.cc
+++ b/arch/alpha/linux_process.cc
@@ -61,7 +61,7 @@ pipeFunc(SyscallDesc *desc, int callnum, Process *process,
 
     // Alpha Linux convention for pipe() is that fd[0] is returned as
     // the return value of the function, and fd[1] is returned in r20.
-    xc->regs.intRegFile[20] = sim_fds[1];
+    xc->setIntReg(20, sim_fds[1]);
     return sim_fds[0];
 }
 
@@ -79,7 +79,7 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process,
     strcpy(name->version, "#1 Mon Aug 18 11:32:15 EDT 2003");
     strcpy(name->machine, "alpha");
 
-    name.copyOut(xc->mem);
+    name.copyOut(xc->getMemPtr());
     return 0;
 }
 
@@ -99,7 +99,7 @@ osf_getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
           TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1));
           // I don't think this exactly matches the HW FPCR
           *fpcr = 0;
-          fpcr.copyOut(xc->mem);
+          fpcr.copyOut(xc->getMemPtr());
           return 0;
       }
 
@@ -125,7 +125,7 @@ osf_setsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
       case 14: { // SSI_IEEE_FP_CONTROL
           TypedBufferArg<uint64_t> fpcr(xc->getSyscallArg(1));
           // I don't think this exactly matches the HW FPCR
-          fpcr.copyIn(xc->mem);
+          fpcr.copyIn(xc->getMemPtr());
           DPRINTFR(SyscallVerbose, "osf_setsysinfo(SSI_IEEE_FP_CONTROL): "
                    " setting FPCR to 0x%x\n", gtoh(*(uint64_t*)fpcr));
           return 0;
diff --git a/arch/alpha/stacktrace.cc b/arch/alpha/stacktrace.cc
index 89b6b73a9..50f2e4d21 100644
--- a/arch/alpha/stacktrace.cc
+++ b/arch/alpha/stacktrace.cc
@@ -44,23 +44,23 @@ ProcessInfo::ProcessInfo(ExecContext *_xc)
 {
     Addr addr = 0;
 
-    if (!xc->system->kernelSymtab->findAddress("thread_info_size", addr))
+    if (!xc->getSystemPtr()->kernelSymtab->findAddress("thread_info_size", addr))
         panic("thread info not compiled into kernel\n");
     thread_info_size = *(int32_t *)vtomem(xc, addr, sizeof(int32_t));
 
-    if (!xc->system->kernelSymtab->findAddress("task_struct_size", addr))
+    if (!xc->getSystemPtr()->kernelSymtab->findAddress("task_struct_size", addr))
         panic("thread info not compiled into kernel\n");
     task_struct_size = *(int32_t *)vtomem(xc, addr, sizeof(int32_t));
 
-    if (!xc->system->kernelSymtab->findAddress("thread_info_task", addr))
+    if (!xc->getSystemPtr()->kernelSymtab->findAddress("thread_info_task", addr))
         panic("thread info not compiled into kernel\n");
     task_off = *(int32_t *)vtomem(xc, addr, sizeof(int32_t));
 
-    if (!xc->system->kernelSymtab->findAddress("task_struct_pid", addr))
+    if (!xc->getSystemPtr()->kernelSymtab->findAddress("task_struct_pid", addr))
         panic("thread info not compiled into kernel\n");
     pid_off = *(int32_t *)vtomem(xc, addr, sizeof(int32_t));
 
-    if (!xc->system->kernelSymtab->findAddress("task_struct_comm", addr))
+    if (!xc->getSystemPtr()->kernelSymtab->findAddress("task_struct_comm", addr))
         panic("thread info not compiled into kernel\n");
     name_off = *(int32_t *)vtomem(xc, addr, sizeof(int32_t));
 }
@@ -126,8 +126,9 @@ StackTrace::trace(ExecContext *_xc, bool is_call)
 
     bool usermode = (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
 
-    Addr pc = xc->regs.npc;
-    bool kernel = xc->system->kernelStart <= pc && pc <= xc->system->kernelEnd;
+    Addr pc = xc->readNextPC();
+    bool kernel = xc->getSystemPtr()->kernelStart <= pc &&
+        pc <= xc->getSystemPtr()->kernelEnd;
 
     if (usermode) {
         stack.push_back(user);
@@ -139,8 +140,8 @@ StackTrace::trace(ExecContext *_xc, bool is_call)
         return;
     }
 
-    SymbolTable *symtab = xc->system->kernelSymtab;
-    Addr ksp = xc->regs.intRegFile[TheISA::StackPointerReg];
+    SymbolTable *symtab = xc->getSystemPtr()->kernelSymtab;
+    Addr ksp = xc->readIntReg(TheISA::StackPointerReg);
     Addr bottom = ksp & ~0x3fff;
     Addr addr;
 
@@ -149,7 +150,7 @@ StackTrace::trace(ExecContext *_xc, bool is_call)
             panic("could not find address %#x", pc);
 
         stack.push_back(addr);
-        pc = xc->regs.pc;
+        pc = xc->readPC();
     }
 
     Addr ra;
@@ -181,8 +182,8 @@ StackTrace::trace(ExecContext *_xc, bool is_call)
             return;
         }
 
-        bool kernel = xc->system->kernelStart <= pc &&
-            pc <= xc->system->kernelEnd;
+        bool kernel = xc->getSystemPtr()->kernelStart <= pc &&
+            pc <= xc->getSystemPtr()->kernelEnd;
         if (!kernel)
             return;
 
@@ -323,8 +324,8 @@ StackTrace::decodePrologue(Addr sp, Addr callpc, Addr func,
 void
 StackTrace::dump()
 {
-    StringWrap name(xc->cpu->name());
-    SymbolTable *symtab = xc->system->kernelSymtab;
+    StringWrap name(xc->getCpuPtr()->name());
+    SymbolTable *symtab = xc->getSystemPtr()->kernelSymtab;
 
     DPRINTFN("------ Stack ------\n");
 
diff --git a/arch/alpha/tlb.cc b/arch/alpha/tlb.cc
index 0f2cedc83..e30a8e595 100644
--- a/arch/alpha/tlb.cc
+++ b/arch/alpha/tlb.cc
@@ -496,9 +496,8 @@ AlphaDTB::fault(MemReqPtr &req, uint64_t flags) const
 Fault
 AlphaDTB::translate(MemReqPtr &req, bool write) const
 {
-    RegFile *regs = &req->xc->regs;
     ExecContext *xc = req->xc;
-    Addr pc = regs->pc;
+    Addr pc = xc->readPC();
 
     AlphaISA::mode_type mode =
         (AlphaISA::mode_type)DTB_CM_CM(xc->readMiscReg(AlphaISA::IPR_DTB_CM));
diff --git a/arch/alpha/tru64_process.cc b/arch/alpha/tru64_process.cc
index 90e8b1139..5f6b802e9 100644
--- a/arch/alpha/tru64_process.cc
+++ b/arch/alpha/tru64_process.cc
@@ -52,7 +52,7 @@ unameFunc(SyscallDesc *desc, int callnum, Process *process,
     strcpy(name->version, "732");
     strcpy(name->machine, "alpha");
 
-    name.copyOut(xc->mem);
+    name.copyOut(xc->getMemPtr());
     return 0;
 }
 
@@ -69,21 +69,21 @@ getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
       case Tru64::GSI_MAX_CPU: {
           TypedBufferArg<uint32_t> max_cpu(xc->getSyscallArg(1));
           *max_cpu = htog((uint32_t)process->numCpus());
-          max_cpu.copyOut(xc->mem);
+          max_cpu.copyOut(xc->getMemPtr());
           return 1;
       }
 
       case Tru64::GSI_CPUS_IN_BOX: {
           TypedBufferArg<uint32_t> cpus_in_box(xc->getSyscallArg(1));
           *cpus_in_box = htog((uint32_t)process->numCpus());
-          cpus_in_box.copyOut(xc->mem);
+          cpus_in_box.copyOut(xc->getMemPtr());
           return 1;
       }
 
       case Tru64::GSI_PHYSMEM: {
           TypedBufferArg<uint64_t> physmem(xc->getSyscallArg(1));
           *physmem = htog((uint64_t)1024 * 1024);	// physical memory in KB
-          physmem.copyOut(xc->mem);
+          physmem.copyOut(xc->getMemPtr());
           return 1;
       }
 
@@ -100,14 +100,14 @@ getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
           infop->cpu_ex_binding = htog(0);
           infop->mhz = htog(667);
 
-          infop.copyOut(xc->mem);
+          infop.copyOut(xc->getMemPtr());
           return 1;
       }
 
       case Tru64::GSI_PROC_TYPE: {
           TypedBufferArg<uint64_t> proc_type(xc->getSyscallArg(1));
           *proc_type = htog((uint64_t)11);
-          proc_type.copyOut(xc->mem);
+          proc_type.copyOut(xc->getMemPtr());
           return 1;
       }
 
@@ -116,14 +116,14 @@ getsysinfoFunc(SyscallDesc *desc, int callnum, Process *process,
           strncpy((char *)bufArg.bufferPtr(),
                   "COMPAQ Professional Workstation XP1000",
                   nbytes);
-          bufArg.copyOut(xc->mem);
+          bufArg.copyOut(xc->getMemPtr());
           return 1;
       }
 
       case Tru64::GSI_CLK_TCK: {
           TypedBufferArg<uint64_t> clk_hz(xc->getSyscallArg(1));
           *clk_hz = htog((uint64_t)1024);
-          clk_hz.copyOut(xc->mem);
+          clk_hz.copyOut(xc->getMemPtr());
           return 1;
       }
 
diff --git a/arch/alpha/vtophys.cc b/arch/alpha/vtophys.cc
index 1d70196c5..40261426d 100644
--- a/arch/alpha/vtophys.cc
+++ b/arch/alpha/vtophys.cc
@@ -95,7 +95,7 @@ vtophys(ExecContext *xc, Addr addr)
             paddr = vaddr;
         } else {
             AlphaISA::PageTableEntry pte =
-                kernel_pte_lookup(xc->physmem, ptbr, vaddr);
+                kernel_pte_lookup(xc->getPhysMemPtr(), ptbr, vaddr);
             if (pte.valid())
                 paddr = pte.paddr() | vaddr.offset();
         }
@@ -110,14 +110,14 @@ vtophys(ExecContext *xc, Addr addr)
 uint8_t *
 ptomem(ExecContext *xc, Addr paddr, size_t len)
 {
-    return xc->physmem->dma_addr(paddr, len);
+    return xc->getPhysMemPtr()->dma_addr(paddr, len);
 }
 
 uint8_t *
 vtomem(ExecContext *xc, Addr vaddr, size_t len)
 {
     Addr paddr = vtophys(xc, vaddr);
-    return xc->physmem->dma_addr(paddr, len);
+    return xc->getPhysMemPtr()->dma_addr(paddr, len);
 }
 
 void
@@ -131,7 +131,7 @@ CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen)
     paddr = vtophys(xc, src);
     len = min((int)(AlphaISA::PageBytes - (paddr & AlphaISA::PageOffset)),
               (int)cplen);
-    dmaaddr = (char *)xc->physmem->dma_addr(paddr, len);
+    dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr, len);
     assert(dmaaddr);
 
     memcpy(dst, dmaaddr, len);
@@ -144,7 +144,8 @@ CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen)
 
     while (cplen > AlphaISA::PageBytes) {
         paddr = vtophys(xc, src);
-        dmaaddr = (char *)xc->physmem->dma_addr(paddr, AlphaISA::PageBytes);
+        dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr,
+                                                        AlphaISA::PageBytes);
         assert(dmaaddr);
 
         memcpy(dst, dmaaddr, AlphaISA::PageBytes);
@@ -155,7 +156,7 @@ CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen)
 
     if (cplen > 0) {
         paddr = vtophys(xc, src);
-        dmaaddr = (char *)xc->physmem->dma_addr(paddr, cplen);
+        dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr, cplen);
         assert(dmaaddr);
 
         memcpy(dst, dmaaddr, cplen);
@@ -173,7 +174,7 @@ CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen)
     paddr = vtophys(xc, dest);
     len = min((int)(AlphaISA::PageBytes - (paddr & AlphaISA::PageOffset)),
               (int)cplen);
-    dmaaddr = (char *)xc->physmem->dma_addr(paddr, len);
+    dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr, len);
     assert(dmaaddr);
 
     memcpy(dmaaddr, src, len);
@@ -186,7 +187,8 @@ CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen)
 
     while (cplen > AlphaISA::PageBytes) {
         paddr = vtophys(xc, dest);
-        dmaaddr = (char *)xc->physmem->dma_addr(paddr, AlphaISA::PageBytes);
+        dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr,
+                                                        AlphaISA::PageBytes);
         assert(dmaaddr);
 
         memcpy(dmaaddr, src, AlphaISA::PageBytes);
@@ -197,7 +199,7 @@ CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen)
 
     if (cplen > 0) {
         paddr = vtophys(xc, dest);
-        dmaaddr = (char *)xc->physmem->dma_addr(paddr, cplen);
+        dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr, cplen);
         assert(dmaaddr);
 
         memcpy(dmaaddr, src, cplen);
@@ -214,7 +216,7 @@ CopyString(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen)
     paddr = vtophys(xc, vaddr);
     len = min((int)(AlphaISA::PageBytes - (paddr & AlphaISA::PageOffset)),
               (int)maxlen);
-    dmaaddr = (char *)xc->physmem->dma_addr(paddr, len);
+    dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr, len);
     assert(dmaaddr);
 
     char *term = (char *)memchr(dmaaddr, 0, len);
@@ -232,7 +234,8 @@ CopyString(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen)
 
     while (maxlen > AlphaISA::PageBytes) {
         paddr = vtophys(xc, vaddr);
-        dmaaddr = (char *)xc->physmem->dma_addr(paddr, AlphaISA::PageBytes);
+        dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr,
+                                                        AlphaISA::PageBytes);
         assert(dmaaddr);
 
         char *term = (char *)memchr(dmaaddr, 0, AlphaISA::PageBytes);
@@ -249,7 +252,7 @@ CopyString(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen)
 
     if (maxlen > 0) {
         paddr = vtophys(xc, vaddr);
-        dmaaddr = (char *)xc->physmem->dma_addr(paddr, maxlen);
+        dmaaddr = (char *)xc->getPhysMemPtr()->dma_addr(paddr, maxlen);
         assert(dmaaddr);
 
         char *term = (char *)memchr(dmaaddr, 0, maxlen);