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authorKorey Sewell <ksewell@umich.edu>2006-04-27 16:44:12 -0400
committerKorey Sewell <ksewell@umich.edu>2006-04-27 16:44:12 -0400
commit316f1f323913482e02f992f9b38a873bbf8588e6 (patch)
tree50d84a5174b8a1c383d25aa4954d89a45b2d207c /arch
parent07d4ad4dbed164818bf7e643c362475084a33d15 (diff)
downloadgem5-316f1f323913482e02f992f9b38a873bbf8588e6.tar.xz
change readPC() + 4 to readNextPC() and the same for NNPC ...
arch/mips/isa/decoder.isa: remove useless cout statements arch/mips/isa_traits.hh: space --HG-- extra : convert_revision : 8b8cf5df6fc3eb92598360343eb887c35cda202d
Diffstat (limited to 'arch')
-rwxr-xr-xarch/isa_parser.py4
-rw-r--r--arch/mips/isa/decoder.isa22
-rw-r--r--arch/mips/isa_traits.hh3
3 files changed, 17 insertions, 12 deletions
diff --git a/arch/isa_parser.py b/arch/isa_parser.py
index 8279a6a5d..921a6fa82 100755
--- a/arch/isa_parser.py
+++ b/arch/isa_parser.py
@@ -1334,7 +1334,7 @@ class NPCOperand(Operand):
return ''
def makeRead(self):
- return '%s = xc->readPC() + 4;\n' % self.base_name
+ return '%s = xc->readNextPC();\n' % self.base_name
def makeWrite(self):
return 'xc->setNextPC(%s);\n' % self.base_name
@@ -1344,7 +1344,7 @@ class NNPCOperand(Operand):
return ''
def makeRead(self):
- return '%s = xc->readPC() + 8;\n' % self.base_name
+ return '%s = xc->readNextNPC();\n' % self.base_name
def makeWrite(self):
return 'xc->setNextNPC(%s);\n' % self.base_name
diff --git a/arch/mips/isa/decoder.isa b/arch/mips/isa/decoder.isa
index d44782a41..4b6e475a8 100644
--- a/arch/mips/isa/decoder.isa
+++ b/arch/mips/isa/decoder.isa
@@ -407,7 +407,6 @@ decode OPCODE_HI default Unknown::unknown() {
format System {
0x2: cfc1({{
- std::cout << "FP Control Reg " << FS << "accessed." << std::endl;
uint32_t fcsr_reg = xc->readMiscReg(FCSR);
switch (FS)
@@ -434,8 +433,6 @@ decode OPCODE_HI default Unknown::unknown() {
}});
0x6: ctc1({{
- std::cout << "FP Control Reg " << FS << "accessed." << std::endl;
-
uint32_t fcsr_reg = xc->readMiscReg(FCSR);
uint32_t temp;
switch (FS)
@@ -553,22 +550,27 @@ decode OPCODE_HI default Unknown::unknown() {
format FloatOp {
0x1: cvt_d_s({{
- int rnd_mode = xc->readMiscReg(FCSR);
- Fd = convert_and_round(Fs.sf,rnd_mode,FP_DOUBLE,FP_SINGLE);
+ //int rnd_mode = xc->readMiscReg(FCSR);
+ Fd = convert_and_round(,DOUBLE_TO_SINGLE);
}});
- 0x4: cvt_w_s({{ int rnd_mode = xc->readMiscReg(FCSR);
- Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE);
+ 0x4: cvt_w_s({{
+ //int rnd_mode = xc->readMiscReg(FCSR);
+ Fd = convert_and_round(Fs.sf,rnd_mode,FP_WORD,FP_SINGLE);
}});
}
//only legal for 64 bit
format Float64Op {
- 0x5: cvt_l_s({{ int rnd_mode = xc->readMiscReg(FCSR);
- Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE);
+ 0x5: cvt_l_s({{
+ //int rnd_mode = xc->readMiscReg(FCSR);
+ Fd = convert_and_round(Fs.sf,rnd_mode,FP_LONG,FP_SINGLE);
}});
- 0x6: cvt_ps_s({{ /*Fd.df = Fs.df<31:0> | Ft.df<31:0>;*/ }});
+ 0x6: cvt_ps_s({{
+ //int rnd_mode = xc->readMiscReg(FCSR);
+ /*Fd.df = Fs.df<31:0> | Ft.df<31:0>;*/
+ }});
}
}
}
diff --git a/arch/mips/isa_traits.hh b/arch/mips/isa_traits.hh
index 2403782d0..e5de675cf 100644
--- a/arch/mips/isa_traits.hh
+++ b/arch/mips/isa_traits.hh
@@ -253,6 +253,7 @@ namespace MipsISA
uint32_t result32;
memcpy(&result32, regSpace + 4 * floatReg, FloatRegSize);
return htog(result32);
+
case DoubleWidth:
uint64_t result64;
memcpy(&result64, regSpace + 4 * floatReg, DoubleRegSize);
@@ -314,6 +315,8 @@ namespace MipsISA
return NoFault;
}
+
+
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);