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authorKorey Sewell <ksewell@umich.edu>2006-05-04 21:21:11 -0400
committerKorey Sewell <ksewell@umich.edu>2006-05-04 21:21:11 -0400
commit34a5732bd3c6a146a62757a50d59b7960c41fc5f (patch)
treeaf4e410ce9cccdc4e26421cd44f4b6a5cec7c3d5 /arch
parentde8eba689164b59679a3e3ef3550bc7abb5ecdce (diff)
downloadgem5-34a5732bd3c6a146a62757a50d59b7960c41fc5f.tar.xz
take-out debug only code
arch/mips/isa/formats/fp.isa: take out debug-only code --HG-- extra : convert_revision : 12c320b4b1432a626acefc496ec7a188c8b3fb66
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/isa/formats/fp.isa2
-rw-r--r--arch/mips/isa_traits.hh14
2 files changed, 0 insertions, 16 deletions
diff --git a/arch/mips/isa/formats/fp.isa b/arch/mips/isa/formats/fp.isa
index fe6bd437f..65b259e20 100644
--- a/arch/mips/isa/formats/fp.isa
+++ b/arch/mips/isa/formats/fp.isa
@@ -32,7 +32,6 @@ output decoder {{
// Primary format for float operate instructions:
def format FloatOp(code, *flags) {{
- code = 'std::cout << "Floating Point Op" << std::endl;\n' + code
iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
@@ -42,7 +41,6 @@ def format FloatOp(code, *flags) {{
// Primary format for float64 operate instructions:
def format Float64Op(code, *flags) {{
- code = 'std::cout << "Floating Point 64" << std::endl;\n' + code
iop = InstObjParams(name, Name, 'MipsStaticInst', CodeBlock(code), flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
diff --git a/arch/mips/isa_traits.hh b/arch/mips/isa_traits.hh
index 105d4c283..efa326e1c 100644
--- a/arch/mips/isa_traits.hh
+++ b/arch/mips/isa_traits.hh
@@ -210,11 +210,6 @@ namespace MipsISA
class FloatRegFile
{
protected:
-
- //Since the floating point registers overlap each other,
- //A generic storage space is used. The float to be returned is
- //pulled from the appropriate section of this region.
- //char regSpace[SingleBytes * NumFloatRegs];
FloatReg32 regs[NumFloatRegs];
public:
@@ -232,14 +227,10 @@ namespace MipsISA
{
case SingleWidth:
void *float_ptr = &regs[floatReg];
- cout << "reading as float, reg." << floatReg << ": " << *(float *) float_ptr << endl;
- cout << "reading as uint32_t, reg." << floatReg << ": " << *(uint32_t *) float_ptr << endl;
return *(float *) float_ptr;
case DoubleWidth:
void *double_ptr = &regs[floatReg];
- cout << "reading as double, reg." << floatReg <<": " << *(double *) double_ptr << endl;
- cout << "reading as uint64_t, reg." << floatReg << hex << ": 0x" << *(uint64_t *) float_ptr << endl;
return *(double *) double_ptr;
default:
@@ -257,8 +248,6 @@ namespace MipsISA
return regs[floatReg];
case DoubleWidth:
- cout << hex << "Combining " << regs[floatReg + 1] << " & " << regs[floatReg + 1] << endl;
- cout << hex << "Returning " << ((FloatReg64)regs[floatReg] << 32 | regs[floatReg + 1]) << endl;
return (FloatReg64)regs[floatReg] << 32 | regs[floatReg + 1];
default:
@@ -302,11 +291,8 @@ namespace MipsISA
break;
case DoubleWidth:
- cout << hex << "Setting val: " << val << endl;
regs[floatReg] = val >> 32;
regs[floatReg + 1] = val;
- cout << dec << "f" << floatReg << ": " << hex<< readRegBits(floatReg,32) << endl;
- cout << dec << "f" << floatReg + 1 << ": " << hex << readRegBits(floatReg+1,32) << endl;
break;
default: