Merge zizzer:/bk/multiarch

into  zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/multiarch

--HG--
rename : arch/alpha/alpha_memory.cc => arch/alpha/memory.cc
rename : arch/alpha/alpha_memory.hh => arch/alpha/memory.hh
extra : convert_revision : c641ba3c1009829b7276279b2dca441be1da5b30

12 files changed, 664 insertions, 496 deletions

diff --git a/arch/alpha/alpha_linux_process.cc b/arch/alpha/linux_process.cc
index 783b189cc..783b189cc 100644
--- a/arch/alpha/alpha_linux_process.cc
+++ b/arch/alpha/linux_process.cc
diff --git a/arch/alpha/alpha_linux_process.hh b/arch/alpha/linux_process.hh
index 7de1b1ac1..7de1b1ac1 100644
--- a/arch/alpha/alpha_linux_process.hh
+++ b/arch/alpha/linux_process.hh
diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/memory.cc
index d00186d95..d00186d95 100644
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/memory.cc
diff --git a/arch/alpha/alpha_memory.hh b/arch/alpha/memory.hh
index de955fa46..de955fa46 100644
--- a/arch/alpha/alpha_memory.hh
+++ b/arch/alpha/memory.hh
diff --git a/arch/alpha/alpha_tru64_process.cc b/arch/alpha/tru64_process.cc
index 8121d3452..8121d3452 100644
--- a/arch/alpha/alpha_tru64_process.cc
+++ b/arch/alpha/tru64_process.cc
diff --git a/arch/alpha/alpha_tru64_process.hh b/arch/alpha/tru64_process.hh
index 051760702..051760702 100644
--- a/arch/alpha/alpha_tru64_process.hh
+++ b/arch/alpha/tru64_process.hh
diff --git a/arch/isa_parser.py b/arch/isa_parser.py
index b92d267c9..7c511a8b3 100755
--- a/arch/isa_parser.py
+++ b/arch/isa_parser.py
@@ -745,9 +745,10 @@ CpuModel('FastCPU', 'fast_cpu_exec.cc',
 CpuModel('FullCPU', 'full_cpu_exec.cc',
          '#include "encumbered/cpu/full/dyn_inst.hh"',
          { 'CPU_exec_context': 'DynInst' })
-CpuModel('AlphaFullCPU', 'alpha_o3_exec.cc',
-         '#include "cpu/o3/alpha_dyn_inst.hh"',
-         { 'CPU_exec_context': 'AlphaDynInst<AlphaSimpleImpl>' })
+
+#CpuModel('AlphaFullCPU', 'alpha_o3_exec.cc',
+#         '#include "cpu/o3/alpha_dyn_inst.hh"',
+#         { 'CPU_exec_context': 'AlphaDynInst<AlphaSimpleImpl>' })
 
 # Expand template with CPU-specific references into a dictionary with
 # an entry for each CPU model name.  The entry key is the model name
diff --git a/arch/mips/faults.cc b/arch/mips/faults.cc
new file mode 100644
index 000000000..e05b3fe59
--- /dev/null
+++ b/arch/mips/faults.cc
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/alpha/faults.hh"
+
+ResetFaultType * const ResetFault =
+    new ResetFaultType("reset", 1, 0x0001);
+ArithmeticFaultType * const ArithmeticFault =
+    new ArithmeticFaultType("arith", 3, 0x0501);
+InterruptFaultType * const InterruptFault =
+    new InterruptFaultType("interrupt", 4, 0x0101);
+NDtbMissFaultType * const NDtbMissFault =
+    new NDtbMissFaultType("dtb_miss_single", 5, 0x0201);
+PDtbMissFaultType * const PDtbMissFault =
+    new PDtbMissFaultType("dtb_miss_double", 6, 0x0281);
+DtbPageFaultType * const DtbPageFault =
+    new DtbPageFaultType("dfault", 8, 0x0381);
+DtbAcvFaultType * const DtbAcvFault =
+    new DtbAcvFaultType("dfault", 9, 0x0381);
+ItbMissFaultType * const ItbMissFault =
+    new ItbMissFaultType("itbmiss", 10, 0x0181);
+ItbPageFaultType * const ItbPageFault =
+    new ItbPageFaultType("itbmiss", 11, 0x0181);
+ItbAcvFaultType * const ItbAcvFault =
+    new ItbAcvFaultType("iaccvio", 12, 0x0081);
+UnimplementedOpcodeFaultType * const UnimplementedOpcodeFault =
+    new UnimplementedOpcodeFaultType("opdec", 13, 0x0481);
+FloatEnableFaultType * const FloatEnableFault =
+    new FloatEnableFaultType("fen", 14, 0x0581);
+PalFaultType * const PalFault =
+    new PalFaultType("pal", 15, 0x2001);
+IntegerOverflowFaultType * const IntegerOverflowFault =
+    new IntegerOverflowFaultType("intover", 16, 0x0501);
+
+Fault ** ListOfFaults[] = {
+        (Fault **)&NoFault,
+        (Fault **)&ResetFault,
+        (Fault **)&MachineCheckFault,
+        (Fault **)&ArithmeticFault,
+        (Fault **)&InterruptFault,
+        (Fault **)&NDtbMissFault,
+        (Fault **)&PDtbMissFault,
+        (Fault **)&AlignmentFault,
+        (Fault **)&DtbPageFault,
+        (Fault **)&DtbAcvFault,
+        (Fault **)&ItbMissFault,
+        (Fault **)&ItbPageFault,
+        (Fault **)&ItbAcvFault,
+        (Fault **)&UnimplementedOpcodeFault,
+        (Fault **)&FloatEnableFault,
+        (Fault **)&PalFault,
+        (Fault **)&IntegerOverflowFault,
+        };
+
+int NumFaults = sizeof(ListOfFaults) / sizeof(Fault **);
diff --git a/arch/mips/faults.hh b/arch/mips/faults.hh
new file mode 100644
index 000000000..4e1cb5ed6
--- /dev/null
+++ b/arch/mips/faults.hh
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ALPHA_FAULTS_HH__
+#define __ALPHA_FAULTS_HH__
+
+#include "sim/faults.hh"
+#include "arch/isa_traits.hh" //For the Addr type
+
+class Garbage;
+class Fault;
+
+class AlphaFault : public Fault
+{
+  public:
+    AlphaFault(char * newName, int newId, Addr newVect)
+        : Fault(newName, newId), vect(newVect)
+    {;}
+
+    Addr vect;
+};
+
+extern class ResetFaultType : public AlphaFault
+{
+  public:
+    ResetFaultType(char * newName, int newId, Addr newVect)
+        : AlphaFault(newName, newId, newVect)
+    {;}
+} * const ResetFault;
+
+extern class ArithmeticFaultType : public AlphaFault
+{
+  public:
+    ArithmeticFaultType(char * newName, int newId, Addr newVect)
+        : AlphaFault(newName, newId, newVect)
+    {;}
+} * const ArithmeticFault;
+
+extern class InterruptFaultType : public AlphaFault
+{
+  public:
+    InterruptFaultType(char * newName, int newId, Addr newVect)
+        : AlphaFault(newName, newId, newVect)
+    {;}
+} * const InterruptFault;
+
+extern class NDtbMissFaultType : public AlphaFault
+{
+  public:
+    NDtbMissFaultType(char * newName, int newId, Addr newVect)
+        : AlphaFault(newName, newId, newVect)
+    {;}
+} * const NDtbMissFault;
+
+extern class PDtbMissFaultType : public AlphaFault
+{
+  public:
+    PDtbMissFaultType(char * newName, int newId, Addr newVect)
+        : AlphaFault(newName, newId, newVect)
+    {;}
+} * const PDtbMissFault;
+
+extern class DtbPageFaultType : public AlphaFault
+{
+  public:
+    DtbPageFaultType(char * newName, int newId, Addr newVect)
+        : AlphaFault(newName, newId, newVect)
+    {;}
+} * const DtbPageFault;
+
+extern class DtbAcvFaultType : public AlphaFault
+{
+  public:
+    DtbAcvFaultType(char * newName, int newId, Addr newVect)
+        : AlphaFault(newName, newId, newVect)
+    {;}
+} * const DtbAcvFault;
+
+extern class ItbMissFaultType : public AlphaFault
+{
+  public:
+    ItbMissFaultType(char * newName, int newId, Addr newVect)
+        : AlphaFault(newName, newId, newVect)
+    {;}
+} * const ItbMissFault;
+
+extern class ItbPageFaultType : public AlphaFault
+{
+  public:
+    ItbPageFaultType(char * newName, int newId, Addr newVect)
+        : AlphaFault(newName, newId, newVect)
+    {;}
+} * const ItbPageFault;
+
+extern class ItbAcvFaultType : public AlphaFault
+{
+  public:
+    ItbAcvFaultType(char * newName, int newId, Addr newVect)
+        : AlphaFault(newName, newId, newVect)
+    {;}
+} * const ItbAcvFault;
+
+extern class UnimplementedOpcodeFaultType : public AlphaFault
+{
+  public:
+    UnimplementedOpcodeFaultType(char * newName, int newId, Addr newVect)
+        : AlphaFault(newName, newId, newVect)
+    {;}
+} * const UnimplementedOpcodeFault;
+
+extern class FloatEnableFaultType : public AlphaFault
+{
+  public:
+    FloatEnableFaultType(char * newName, int newId, Addr newVect)
+        : AlphaFault(newName, newId, newVect)
+    {;}
+} * const FloatEnableFault;
+
+extern class PalFaultType : public AlphaFault
+{
+  public:
+    PalFaultType(char * newName, int newId, Addr newVect)
+        : AlphaFault(newName, newId, newVect)
+    {;}
+} * const PalFault;
+
+extern class IntegerOverflowFaultType : public AlphaFault
+{
+  public:
+    IntegerOverflowFaultType(char * newName, int newId, Addr newVect)
+        : AlphaFault(newName, newId, newVect)
+    {;}
+} * const IntegerOverflowFault;
+
+extern Fault ** ListOfFaults[];
+extern int NumFaults;
+
+#endif // __FAULTS_HH__
diff --git a/arch/mips/isa/base.isa b/arch/mips/isa/base.isa
index 846d161b9..49de59e55 100644
--- a/arch/mips/isa/base.isa
+++ b/arch/mips/isa/base.isa
@@ -7,57 +7,81 @@
 
 //Outputs to decoder.hh
 output header {{
-        /**
-         * Base class for all MIPS static instructions.
-         */
-        class MipsStaticInst : public StaticInst<MIPSISA>
+    /**
+     * Base class for all MIPS static instructions.
+     */
+    class MipsStaticInst : public StaticInst
+    {
+      protected:
+
+        /// Make MipsISA register dependence tags directly visible in
+        /// this class and derived classes.  Maybe these should really
+        /// live here and not in the MipsISA namespace.
+        enum DependenceTags {
+            FP_Base_DepTag = MipsISA::FP_Base_DepTag,
+            Fpcr_DepTag = MipsISA::Fpcr_DepTag,
+            Uniq_DepTag = MipsISA::Uniq_DepTag,
+            IPR_Base_DepTag = MipsISA::IPR_Base_DepTag
+        };
+
+        // Constructor
+        MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
+            : StaticInst(mnem, _machInst, __opClass)
         {
-        protected:
+        }
 
-                // Constructor.
-                MipsStaticInst(const char *mnem, MachInst _machInst, OpClass __opClass)
-                    : StaticInst<MIPSISA>(mnem, _machInst, __opClass)
-                {
-                }
+        /// Print a register name for disassembly given the unique
+        /// dependence tag number (FP or int).
+        void printReg(std::ostream &os, int reg) const;
 
-                std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
-        };
+        std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
+    };
 
 }};
 
 //Ouputs to decoder.cc
 output decoder {{
 
-        std::string MipsStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+    void MipsStaticInst::printReg(std::ostream &os, int reg) const
+    {
+        if (reg < FP_Base_DepTag) {
+            ccprintf(os, "r%d", reg);
+        }
+        else {
+            ccprintf(os, "f%d", reg - FP_Base_DepTag);
+        }
+    }
+
+    std::string MipsStaticInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const
+    {
+        std::stringstream ss;
+
+        ccprintf(ss, "%-10s ", mnemonic);
+
+        // just print the first two source regs... if there's
+        // a third one, it's a read-modify-write dest (Rc),
+        // e.g. for CMOVxx
+        if(_numSrcRegs > 0)
+        {
+            printReg(ss, _srcRegIdx[0]);
+        }
+        if(_numSrcRegs > 1)
         {
-                std::stringstream ss;
-
-                ccprintf(ss, "%-10s ", mnemonic);
-
-                // just print the first two source regs... if there's
-                // a third one, it's a read-modify-write dest (Rc),
-                // e.g. for CMOVxx
-                if(_numSrcRegs > 0)
-                {
-                        printReg(ss, _srcRegIdx[0]);
-                }
-                if(_numSrcRegs > 1)
-                {
-                        ss << ",";
-                        printReg(ss, _srcRegIdx[1]);
-                }
-
-                // just print the first dest... if there's a second one,
-                // it's generally implicit
-                if(_numDestRegs > 0)
-                {
-                        if(_numSrcRegs > 0)
-                                ss << ",";
-                        printReg(ss, _destRegIdx[0]);
-                }
-
-                return ss.str();
+            ss << ",";
+            printReg(ss, _srcRegIdx[1]);
         }
 
+        // just print the first dest... if there's a second one,
+        // it's generally implicit
+        if(_numDestRegs > 0)
+        {
+            if(_numSrcRegs > 0)
+                ss << ",";
+            printReg(ss, _destRegIdx[0]);
+        }
+
+        return ss.str();
+    }
+
 }};
 
diff --git a/arch/mips/isa_traits.cc b/arch/mips/isa_traits.cc
index 90a85feb6..02a857af7 100644
--- a/arch/mips/isa_traits.cc
+++ b/arch/mips/isa_traits.cc
@@ -27,32 +27,121 @@
  */
 
 #include "arch/mips/isa_traits.hh"
+#include "config/full_system.hh"
 #include "cpu/static_inst.hh"
 #include "sim/serialize.hh"
 
-// Alpha UNOP (ldq_u r31,0(r0))
-// @todo: fix to MIPS specific
+using namespace MipsISA;
+
+const Addr MipsISA::PageShift = 13;
+const Addr MipsISA::PageBytes = ULL(1) << PageShift;
+const Addr MipsISA::PageMask = ~(PageBytes - 1);
+const Addr MipsISA::PageOffset = PageBytes - 1;
+
+#if FULL_SYSTEM
+
+////////////////////////////////////////////////////////////////////////
+//
+//  Translation stuff
+//
+
+const Addr MipsISA::PteShift = 3;
+const Addr MipsISA::NPtePageShift = PageShift - PteShift;
+const Addr MipsISA::NPtePage = ULL(1) << NPtePageShift;
+const Addr MipsISA::PteMask = NPtePage - 1;
+
+// User Virtual
+const Addr MipsISA::USegBase = ULL(0x0);
+const Addr MipsISA::USegEnd = ULL(0x000003ffffffffff);
+
+// Kernel Direct Mapped
+const Addr MipsISA::K0SegBase = ULL(0xfffffc0000000000);
+const Addr MipsISA::K0SegEnd = ULL(0xfffffdffffffffff);
+
+// Kernel Virtual
+const Addr MipsISA::K1SegBase = ULL(0xfffffe0000000000);
+const Addr MipsISA::K1SegEnd = ULL(0xffffffffffffffff);
+
+#endif
+
+// Mips UNOP (ldq_u r31,0(r0))
 const MachInst MipsISA::NoopMachInst = 0x2ffe0000;
 
+static inline Addr
+TruncPage(Addr addr)
+{ return addr & ~(MipsISA::PageBytes - 1); }
+
+static inline Addr
+RoundPage(Addr addr)
+{ return (addr + MipsISA::PageBytes - 1) & ~(MipsISA::PageBytes - 1); }
 void
-MipsISA::RegFile::serialize(std::ostream &os)
+RegFile::serialize(std::ostream &os)
 {
-    intRegFile.serialize(os);
-    floatRegFile.serialize(os);
-    miscRegs.serialize(os);
+    SERIALIZE_ARRAY(intRegFile, NumIntRegs);
+    SERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs);
+    SERIALIZE_SCALAR(miscRegs.fpcr);
+    SERIALIZE_SCALAR(miscRegs.uniq);
+    SERIALIZE_SCALAR(miscRegs.lock_flag);
+    SERIALIZE_SCALAR(miscRegs.lock_addr);
     SERIALIZE_SCALAR(pc);
     SERIALIZE_SCALAR(npc);
+#if FULL_SYSTEM
+    SERIALIZE_ARRAY(palregs, NumIntRegs);
+    SERIALIZE_ARRAY(ipr, NumInternalProcRegs);
+    SERIALIZE_SCALAR(intrflag);
+    SERIALIZE_SCALAR(pal_shadow);
+#endif
 }
 
 
 void
-MipsISA::RegFile::unserialize(Checkpoint *cp, const std::string &section)
+RegFile::unserialize(Checkpoint *cp, const std::string &section)
 {
-    intRegFile.unserialize(cp, section);
-    floatRegFile.unserialize(cp, section);
-    miscRegs.unserialize(cp, section);
+    UNSERIALIZE_ARRAY(intRegFile, NumIntRegs);
+    UNSERIALIZE_ARRAY(floatRegFile.q, NumFloatRegs);
+    UNSERIALIZE_SCALAR(miscRegs.fpcr);
+    UNSERIALIZE_SCALAR(miscRegs.uniq);
+    UNSERIALIZE_SCALAR(miscRegs.lock_flag);
+    UNSERIALIZE_SCALAR(miscRegs.lock_addr);
     UNSERIALIZE_SCALAR(pc);
     UNSERIALIZE_SCALAR(npc);
+#if FULL_SYSTEM
+    UNSERIALIZE_ARRAY(palregs, NumIntRegs);
+    UNSERIALIZE_ARRAY(ipr, NumInternalProcRegs);
+    UNSERIALIZE_SCALAR(intrflag);
+    UNSERIALIZE_SCALAR(pal_shadow);
+#endif
+}
+
+
+#if FULL_SYSTEM
+void
+PTE::serialize(std::ostream &os)
+{
+    SERIALIZE_SCALAR(tag);
+    SERIALIZE_SCALAR(ppn);
+    SERIALIZE_SCALAR(xre);
+    SERIALIZE_SCALAR(xwe);
+    SERIALIZE_SCALAR(asn);
+    SERIALIZE_SCALAR(asma);
+    SERIALIZE_SCALAR(fonr);
+    SERIALIZE_SCALAR(fonw);
+    SERIALIZE_SCALAR(valid);
+}
+
+
+void
+PTE::unserialize(Checkpoint *cp, const std::string &section)
+{
+    UNSERIALIZE_SCALAR(tag);
+    UNSERIALIZE_SCALAR(ppn);
+    UNSERIALIZE_SCALAR(xre);
+    UNSERIALIZE_SCALAR(xwe);
+    UNSERIALIZE_SCALAR(asn);
+    UNSERIALIZE_SCALAR(asma);
+    UNSERIALIZE_SCALAR(fonr);
+    UNSERIALIZE_SCALAR(fonw);
+    UNSERIALIZE_SCALAR(valid);
 }
 
 #endif //FULL_SYSTEM
diff --git a/arch/mips/isa_traits.hh b/arch/mips/isa_traits.hh
index 603af60e2..c636cd241 100644
--- a/arch/mips/isa_traits.hh
+++ b/arch/mips/isa_traits.hh
@@ -29,13 +29,14 @@
 #ifndef __ARCH_MIPS_ISA_TRAITS_HH__
 #define __ARCH_MIPS_ISA_TRAITS_HH__
 
-//This makes sure the big endian versions of certain functions are used.
 namespace LittleEndianGuest {}
-using namespace LittleEndianGuest
+using namespace LittleEndianGuest;
 
-#include "arch/mips/faults.hh"
+//#include "arch/mips/faults.hh"
 #include "base/misc.hh"
+#include "config/full_system.hh"
 #include "sim/host.hh"
+#include "sim/faults.hh"
 
 class FastCPU;
 class FullCPU;
@@ -43,453 +44,260 @@ class Checkpoint;
 
 #define TARGET_MIPS
 
-template <class ISA> class StaticInst;
-template <class ISA> class StaticInstPtr;
+class StaticInst;
+class StaticInstPtr;
 
-//namespace MIPS34K
-//{
-//	int DTB_ASN_ASN(uint64_t reg);
-//	int ITB_ASN_ASN(uint64_t reg);
-//}
+namespace MIPS34K {
+int DTB_ASN_ASN(uint64_t reg);
+int ITB_ASN_ASN(uint64_t reg);
+}
 
-class MipsISA
+namespace MipsISA
 {
-        public:
-
-        typedef uint32_t MachInst;
-        typedef uint64_t Addr;
-        typedef uint8_t  RegIndex;
-
-        enum
-        {
-                MemoryEnd = 0xffffffffffffffffULL,
-
-                NumFloatRegs = 32,
-                NumMiscRegs = 32,
 
-                MaxRegsOfAnyType = 32,
-                // Static instruction parameters
-                MaxInstSrcRegs = 3,
-                MaxInstDestRegs = 2,
-
-                // Maximum trap level
-                MaxTL = 4
+    typedef uint32_t MachInst;
+//    typedef uint64_t Addr;
+    typedef uint8_t  RegIndex;
+
+    enum {
+        MemoryEnd = 0xffffffffffffffffULL,
+
+        NumIntRegs = 32,
+        NumFloatRegs = 32,
+        NumMiscRegs = 32,
+
+        MaxRegsOfAnyType = 32,
+        // Static instruction parameters
+        MaxInstSrcRegs = 3,
+        MaxInstDestRegs = 2,
+
+        // semantically meaningful register indices
+        ZeroReg = 31,	// architecturally meaningful
+        // the rest of these depend on the ABI
+        StackPointerReg = 30,
+        GlobalPointerReg = 29,
+        ProcedureValueReg = 27,
+        ReturnAddressReg = 26,
+        ReturnValueReg = 0,
+        FramePointerReg = 15,
+        ArgumentReg0 = 16,
+        ArgumentReg1 = 17,
+        ArgumentReg2 = 18,
+        ArgumentReg3 = 19,
+        ArgumentReg4 = 20,
+        ArgumentReg5 = 21,
+
+        LogVMPageSize = 13,	// 8K bytes
+        VMPageSize = (1 << LogVMPageSize),
+
+        BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
+
+        WordBytes = 4,
+        HalfwordBytes = 2,
+        ByteBytes = 1,
+        DepNA = 0,
+    };
+
+    // These enumerate all the registers for dependence tracking.
+    enum DependenceTags {
+        // 0..31 are the integer regs 0..31
+        // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
+        FP_Base_DepTag = 32,
+        Ctrl_Base_DepTag = 64,
+        Fpcr_DepTag = 64,		// floating point control register
+        Uniq_DepTag = 65,
+        IPR_Base_DepTag = 66
+    };
+
+    typedef uint64_t IntReg;
+    typedef IntReg IntRegFile[NumIntRegs];
+
+    // floating point register file entry type
+    typedef union {
+        uint64_t q;
+        double d;
+    } FloatReg;
+
+    typedef union {
+        uint64_t q[NumFloatRegs];	// integer qword view
+        double d[NumFloatRegs];		// double-precision floating point view
+    } FloatRegFile;
+
+    // control register file contents
+    typedef uint64_t MiscReg;
+    typedef struct {
+        uint64_t	fpcr;		// floating point condition codes
+        uint64_t	uniq;		// process-unique register
+        bool		lock_flag;	// lock flag for LL/SC
+        Addr		lock_addr;	// lock address for LL/SC
+    } MiscRegFile;
+
+extern const Addr PageShift;
+extern const Addr PageBytes;
+extern const Addr PageMask;
+extern const Addr PageOffset;
+
+#if FULL_SYSTEM
+
+    typedef uint64_t InternalProcReg;
+
+#include "arch/mips/isa_fullsys_traits.hh"
+
+#else
+    enum {
+        NumInternalProcRegs = 0
+    };
+#endif
 
-                // semantically meaningful register indices
-                ZeroReg = 0,	// architecturally meaningful
-                // the rest of these depend on the ABI
-        }
-        typedef uint64_t IntReg;
+    enum {
+        TotalNumRegs =
+        NumIntRegs + NumFloatRegs + NumMiscRegs + NumInternalProcRegs
+    };
+
+    enum {
+        TotalDataRegs = NumIntRegs + NumFloatRegs
+    };
+
+    typedef union {
+        IntReg  intreg;
+        FloatReg   fpreg;
+        MiscReg ctrlreg;
+    } AnyReg;
+
+    struct RegFile {
+        IntRegFile intRegFile;		// (signed) integer register file
+        FloatRegFile floatRegFile;	// floating point register file
+        MiscRegFile miscRegs;		// control register file
+        Addr pc;			// program counter
+        Addr npc;			// next-cycle program counter
+#if FULL_SYSTEM
+        IntReg palregs[NumIntRegs];	// PAL shadow registers
+        InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
+        int intrflag;			// interrupt flag
+        bool pal_shadow;		// using pal_shadow registers
+        inline int instAsid() { return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]); }
+        inline int dataAsid() { return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]); }
+#endif // FULL_SYSTEM
+
+        void serialize(std::ostream &os);
+        void unserialize(Checkpoint *cp, const std::string &section);
+    };
+
+    StaticInstPtr decodeInst(MachInst);
+
+    // return a no-op instruction... used for instruction fetch faults
+    extern const MachInst NoopMachInst;
+
+    enum annotes {
+        ANNOTE_NONE = 0,
+        // An impossible number for instruction annotations
+        ITOUCH_ANNOTE = 0xffffffff,
+    };
+
+    static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
+        panic("register classification not implemented");
+        return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
+    }
+
+    static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
+        panic("register classification not implemented");
+        return (reg >= 9 && reg <= 15);
+    }
+
+    static inline bool isCallerSaveFloatRegister(unsigned int reg) {
+        panic("register classification not implemented");
+        return false;
+    }
+
+    static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
+        panic("register classification not implemented");
+        return false;
+    }
+
+    static inline Addr alignAddress(const Addr &addr,
+                                         unsigned int nbytes) {
+        return (addr & ~(nbytes - 1));
+    }
+
+    // Instruction address compression hooks
+    static inline Addr realPCToFetchPC(const Addr &addr) {
+        return addr;
+    }
+
+    static inline Addr fetchPCToRealPC(const Addr &addr) {
+        return addr;
+    }
+
+    // the size of "fetched" instructions (not necessarily the size
+    // of real instructions for PISA)
+    static inline size_t fetchInstSize() {
+        return sizeof(MachInst);
+    }
+
+    static inline MachInst makeRegisterCopy(int dest, int src) {
+        panic("makeRegisterCopy not implemented");
+        return 0;
+    }
+
+    // Machine operations
+
+    void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
+                               int regnum);
+
+    void restoreMachineReg(RegFile &regs, const AnyReg &reg,
+                                  int regnum);
+
+#if 0
+    static void serializeSpecialRegs(const Serializable::Proxy &proxy,
+                                     const RegFile &regs);
+
+    static void unserializeSpecialRegs(const IniFile *db,
+                                       const std::string &category,
+                                       ConfigNode *node,
+                                       RegFile &regs);
+#endif
 
-        class IntRegFile
-        {
-        private:
-                //For right now, let's pretend the register file is static
-                IntReg regs[32];
-        public:
-                IntReg & operator [] (RegIndex index)
-                {
-                        //Don't allow indexes outside of the 32 registers
-                        index &= 0x1F
-                        return regs[index];
-                }
-        };
-
-        void inline serialize(std::ostream & os)
-        {
-                SERIALIZE_ARRAY(regs, 32);
-        }
-
-        void inline unserialize(Checkpoint &*cp, const std::string &section)
-        {
-                UNSERIALIZE_ARRAY(regs, 32);
-        }
-
-        class FloatRegFile
-        {
-        private:
-                //By using the largest data type, we ensure everything
-                //is aligned correctly in memory
-                union
-                {
-                        double double rawRegs[16];
-                        uint64_t regDump[32];
-                };
-                class QuadRegs
-                {
-                        private:
-                                FloatRegFile * parent;
-                        public:
-                                QuadRegs(FloatRegFile * p) : parent(p) {;}
-                                double double & operator [] (RegIndex index)
-                                {
-                                        //Quad floats are index by the single
-                                        //precision register the start on,
-                                        //and only 16 should be accessed
-                                        index = (index >> 2) & 0xF;
-                                        return parent->rawRegs[index];
-                                }
-                };
-                class DoubleRegs
-                {
-                        private:
-                                FloatRegFile * parent;
-                        public:
-                                DoubleRegs(FloatRegFile * p) : parent(p) {;}
-                                double & operator [] (RegIndex index)
-                                {
-                                        //Double floats are index by the single
-                                        //precision register the start on,
-                                        //and only 32 should be accessed
-                                        index = (index >> 1) & 0x1F
-                                        return ((double [])parent->rawRegs)[index];
-                                }
-                }
-                class SingleRegs
-                {
-                        private:
-                                FloatRegFile * parent;
-                                public:
-                                SingleRegs(FloatRegFile * p) : parent(p) {;}
-                                double & operator [] (RegFile index)
-                                {
-                                        //Only 32 single floats should be accessed
-                                        index &= 0x1F
-                                        return ((float [])parent->rawRegs)[index];
-                                }
-                }
-        public:
-                void inline serialize(std::ostream & os)
-                {
-                        SERIALIZE_ARRAY(regDump, 32);
-                }
-
-                void inline unserialize(Checkpoint &* cp, std::string & section)
-                {
-                        UNSERIALIZE_ARRAY(regDump, 32);
-                }
-
-                QuadRegs quadRegs;
-                DoubleRegs doubleRegs;
-                SingleRegs singleRegs;
-                FloatRegFile() : quadRegs(this), doubleRegs(this), singleRegs(this)
-                {;}
-        };
-
-        // control register file contents
-        typedef uint64_t MiscReg;
-        // The control registers, broken out into fields
-        class MiscRegFile
-        {
-        public:
-                union
-                {
-                        uint16_t pstate;		// Process State Register
-                        struct
-                        {
-                                uint16_t ag:1;		// Alternate Globals
-                                uint16_t ie:1;		// Interrupt enable
-                                uint16_t priv:1;	// Privelege mode
-                                uint16_t am:1;		// Address mask
-                                uint16_t pef:1;		// PSTATE enable floating-point
-                                uint16_t red:1;		// RED (reset, error, debug) state
-                                uint16_t mm:2;		// Memory Model
-                                uint16_t tle:1;		// Trap little-endian
-                                uint16_t cle:1;		// Current little-endian
-                        } pstateFields;
-                }
-                uint64_t tba;		// Trap Base Address
-                union
-                {
-                        uint64_t y;		// Y (used in obsolete multiplication)
-                        struct
-                        {
-                                uint64_t value:32;	// The actual value stored in y
-                                const uint64_t :32;	// reserved bits
-                        } yFields;
-                }
-                uint8_t pil;		// Process Interrupt Register
-                uint8_t cwp;		// Current Window Pointer
-                uint16_t tt[MaxTL];	// Trap Type (Type of trap which occured on the previous level)
-                union
-                {
-                        uint8_t	ccr;		// Condition Code Register
-                        struct
-                        {
-                                union
-                                {
-                                        uint8_t icc:4;	// 32-bit condition codes
-                                        struct
-                                        {
-                                                uint8_t c:1;	// Carry
-                                                uint8_t v:1;	// Overflow
-                                                uint8_t z:1;	// Zero
-                                                uint8_t n:1;	// Negative
-                                        } iccFields:4;
-                                } :4;
-                                union
-                                {
-                                        uint8_t xcc:4;	// 64-bit condition codes
-                                        struct
-                                        {
-                                                uint8_t c:1;	// Carry
-                                                uint8_t v:1;	// Overflow
-                                                uint8_t z:1;	// Zero
-                                                uint8_t n:1;	// Negative
-                                        } xccFields:4;
-                                } :4;
-                        } ccrFields;
-                }
-                uint8_t asi;		// Address Space Identifier
-                uint8_t tl;		// Trap Level
-                uint64_t tpc[MaxTL];	// Trap Program Counter (value from previous trap level)
-                uint64_t tnpc[MaxTL];	// Trap Next Program Counter (value from previous trap level)
-                union
-                {
-                        uint64_t tstate[MaxTL];	// Trap State
-                        struct
-                        {
-                                //Values are from previous trap level
-                                uint64_t cwp:5;		// Current Window Pointer
-                                const uint64_t :2;	// Reserved bits
-                                uint64_t pstate:10;	// Process State
-                                const uint64_t :6;	// Reserved bits
-                                uint64_t asi:8;		// Address Space Identifier
-                                uint64_t ccr:8;		// Condition Code Register
-                        } tstateFields[MaxTL];
-                }
-                union
-                {
-                        uint64_t	tick;		// Hardware clock-tick counter
-                        struct
-                        {
-                                uint64_t counter:63;	// Clock-tick count
-                                uint64_t npt:1;		// Non-priveleged trap
-                        } tickFields;
-                }
-                uint8_t cansave;	// Savable windows
-                uint8_t canrestore;	// Restorable windows
-                uint8_t otherwin;	// Other windows
-                uint8_t cleanwin;	// Clean windows
-                union
-                {
-                        uint8_t wstate;		// Window State
-                        struct
-                        {
-                                uint8_t normal:3;	// Bits TT<4:2> are set to on a normal
-                                                        // register window trap
-                                uint8_t other:3;	// Bits TT<4:2> are set to on an "otherwin"
-                                                        // register window trap
-                        } wstateFields;
-                }
-                union
-                {
-                        uint64_t ver;		// Version
-                        struct
-                        {
-                                uint64_t maxwin:5;	// Max CWP value
-                                const uint64_t :2;	// Reserved bits
-                                uint64_t maxtl:8;	// Maximum trap level
-                                const uint64_t :8;	// Reserved bits
-                                uint64_t mask:8;	// Processor mask set revision number
-                                uint64_t impl:16;	// Implementation identification number
-                                uint64_t manuf:16;	// Manufacturer code
-                        } verFields;
-                }
-                union
-                {
-                        uint64_t	fsr;	// Floating-Point State Register
-                        struct
-                        {
-                                union
-                                {
-                                        uint64_t cexc:5;	// Current excpetion
-                                        struct
-                                        {
-                                                uint64_t nxc:1;		// Inexact
-                                                uint64_t dzc:1;		// Divide by zero
-                                                uint64_t ufc:1;		// Underflow
-                                                uint64_t ofc:1;		// Overflow
-                                                uint64_t nvc:1;		// Invalid operand
-                                        } cexecFields:5;
-                                } :5;
-                                union
-                                {
-                                        uint64_t aexc:5;		// Accrued exception
-                                        struct
-                                        {
-                                                uint64_t nxc:1;		// Inexact
-                                                uint64_t dzc:1;		// Divide by zero
-                                                uint64_t ufc:1;		// Underflow
-                                                uint64_t ofc:1;		// Overflow
-                                                uint64_t nvc:1;		// Invalid operand
-                                        } aexecFields:5;
-                                } :5;
-                                uint64_t fcc0:2;		// Floating-Point condtion codes
-                                const uint64_t :1;		// Reserved bits
-                                uint64_t qne:1;			// Deferred trap queue not empty
-                                                                // with no queue, it should read 0
-                                uint64_t ftt:3;			// Floating-Point trap type
-                                uint64_t ver:3;			// Version (of the FPU)
-                                const uint64_t :2;		// Reserved bits
-                                uint64_t ns:1;			// Nonstandard floating point
-                                union
-                                {
-                                        uint64_t tem:5;			// Trap Enable Mask
-                                        struct
-                                        {
-                                                uint64_t nxm:1;		// Inexact
-                                                uint64_t dzm:1;		// Divide by zero
-                                                uint64_t ufm:1;		// Underflow
-                                                uint64_t ofm:1;		// Overflow
-                                                uint64_t nvm:1;		// Invalid operand
-                                        } temFields:5;
-                                } :5;
-                                const uint64_t :2;		// Reserved bits
-                                uint64_t rd:2;			// Rounding direction
-                                uint64_t fcc1:2;		// Floating-Point condition codes
-                                uint64_t fcc2:2;		// Floating-Point condition codes
-                                uint64_t fcc3:2;		// Floating-Point condition codes
-                                const uint64_t :26;		// Reserved bits
-                        } fsrFields;
-                }
-                union
-                {
-                        uint8_t		fprs;	// Floating-Point Register State
-                        struct
-                        {
-                                dl:1;		// Dirty lower
-                                du:1;		// Dirty upper
-                                fef:1;		// FPRS enable floating-Point
-                        } fprsFields;
-                };
-
-                void serialize(std::ostream & os)
-                {
-                        SERIALIZE_SCALAR(pstate);
-                        SERIAlIZE_SCALAR(tba);
-                        SERIALIZE_SCALAR(y);
-                        SERIALIZE_SCALAR(pil);
-                        SERIALIZE_SCALAR(cwp);
-                        SERIALIZE_ARRAY(tt, MaxTL);
-                        SERIALIZE_SCALAR(ccr);
-                        SERIALIZE_SCALAR(asi);
-                        SERIALIZE_SCALAR(tl);
-                        SERIALIZE_SCALAR(tpc);
-                        SERIALIZE_SCALAR(tnpc);
-                        SERIALIZE_ARRAY(tstate, MaxTL);
-                        SERIALIZE_SCALAR(tick);
-                        SERIALIZE_SCALAR(cansave);
-                        SERIALIZE_SCALAR(canrestore);
-                        SERIALIZE_SCALAR(otherwin);
-                        SERIALIZE_SCALAR(cleanwin);
-                        SERIALIZE_SCALAR(wstate);
-                        SERIALIZE_SCALAR(ver);
-                        SERIALIZE_SCALAR(fsr);
-                        SERIALIZE_SCALAR(fprs);
-                }
-
-                void unserialize(Checkpoint &* cp, std::string & section)
-                {
-                        UNSERIALIZE_SCALAR(pstate);
-                        UNSERIAlIZE_SCALAR(tba);
-                        UNSERIALIZE_SCALAR(y);
-                        UNSERIALIZE_SCALAR(pil);
-                        UNSERIALIZE_SCALAR(cwp);
-                        UNSERIALIZE_ARRAY(tt, MaxTL);
-                        UNSERIALIZE_SCALAR(ccr);
-                        UNSERIALIZE_SCALAR(asi);
-                        UNSERIALIZE_SCALAR(tl);
-                        UNSERIALIZE_SCALAR(tpc);
-                        UNSERIALIZE_SCALAR(tnpc);
-                        UNSERIALIZE_ARRAY(tstate, MaxTL);
-                        UNSERIALIZE_SCALAR(tick);
-                        UNSERIALIZE_SCALAR(cansave);
-                        UNSERIALIZE_SCALAR(canrestore);
-                        UNSERIALIZE_SCALAR(otherwin);
-                        UNSERIALIZE_SCALAR(cleanwin);
-                        UNSERIALIZE_SCALAR(wstate);
-                        UNSERIALIZE_SCALAR(ver);
-                        UNSERIALIZE_SCALAR(fsr);
-                        UNSERIALIZE_SCALAR(fprs);
-                }
-        };
-
-        typedef union
-        {
-                IntReg  intreg;
-                FloatReg   fpreg;
-                MiscReg ctrlreg;
-        } AnyReg;
-
-        struct RegFile
-        {
-                IntRegFile intRegFile;		// (signed) integer register file
-                FloatRegFile floatRegFile;	// floating point register file
-                MiscRegFile miscRegFile;	// control register file
-
-                Addr pc;		// Program Counter
-                Addr npc;		// Next Program Counter
-            Addr nnpc;                  // Next next program Counter
-
-
-                void serialize(std::ostream &os);
-                void unserialize(Checkpoint *cp, const std::string &section);
-        };
-
-        static StaticInstPtr<MipsISA> decodeInst(MachInst);
-
-        // return a no-op instruction... used for instruction fetch faults
-        static const MachInst NoopMachInst;
-
-        // Instruction address compression hooks
-        static inline Addr realPCToFetchPC(const Addr &addr)
-        {
-                return addr;
-        }
-
-        static inline Addr fetchPCToRealPC(const Addr &addr)
-        {
-                return addr;
-        }
-
-        // the size of "fetched" instructions (not necessarily the size
-        // of real instructions for PISA)
-        static inline size_t fetchInstSize()
-        {
-                return sizeof(MachInst);
-        }
-
-        /**
-         * Function to insure ISA semantics about 0 registers.
-         * @param xc The execution context.
-         */
-        template <class XC>
-        static void zeroRegisters(XC *xc);
+    /**
+     * Function to insure ISA semantics about 0 registers.
+     * @param xc The execution context.
+     */
+    template <class XC>
+    void zeroRegisters(XC *xc);
+
+
+//typedef MipsISA TheISA;
+
+//typedef TheISA::MachInst MachInst;
+//typedef TheISA::Addr Addr;
+//typedef TheISA::RegIndex RegIndex;
+//typedef TheISA::IntReg IntReg;
+//typedef TheISA::IntRegFile IntRegFile;
+//typedef TheISA::FloatReg FloatReg;
+//typedef TheISA::FloatRegFile FloatRegFile;
+//typedef TheISA::MiscReg MiscReg;
+//typedef TheISA::MiscRegFile MiscRegFile;
+//typedef TheISA::AnyReg AnyReg;
+//typedef TheISA::RegFile RegFile;
+
+//const int NumIntRegs   = TheISA::NumIntRegs;
+//const int NumFloatRegs = TheISA::NumFloatRegs;
+//const int NumMiscRegs  = TheISA::NumMiscRegs;
+//const int TotalNumRegs = TheISA::TotalNumRegs;
+//const int VMPageSize   = TheISA::VMPageSize;
+//const int LogVMPageSize   = TheISA::LogVMPageSize;
+//const int ZeroReg = TheISA::ZeroReg;
+//const int StackPointerReg = TheISA::StackPointerReg;
+//const int GlobalPointerReg = TheISA::GlobalPointerReg;
+//const int ReturnAddressReg = TheISA::ReturnAddressReg;
+//const int ReturnValueReg = TheISA::ReturnValueReg;
+//const int ArgumentReg0 = TheISA::ArgumentReg0;
+//const int ArgumentReg1 = TheISA::ArgumentReg1;
+//const int ArgumentReg2 = TheISA::ArgumentReg2;
+//const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
+const Addr MaxAddr = (Addr)-1;
 };
 
-
-typedef MIPSISA TheISA;
-
-typedef TheISA::MachInst MachInst;
-typedef TheISA::Addr Addr;
-typedef TheISA::RegIndex RegIndex;
-typedef TheISA::IntReg IntReg;
-typedef TheISA::IntRegFile IntRegFile;
-typedef TheISA::FloatReg FloatReg;
-typedef TheISA::FloatRegFile FloatRegFile;
-typedef TheISA::MiscReg MiscReg;
-typedef TheISA::MiscRegFile MiscRegFile;
-typedef TheISA::AnyReg AnyReg;
-typedef TheISA::RegFile RegFile;
-
-const int VMPageSize   = TheISA::VMPageSize;
-const int LogVMPageSize   = TheISA::LogVMPageSize;
-const int ZeroReg = TheISA::ZeroReg;
-const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
-const int MaxAddr = (Addr)-1;
-
-#ifndef FULL_SYSTEM
+#if !FULL_SYSTEM
 class SyscallReturn {
         public:
            template <class T>
@@ -526,7 +334,10 @@ class SyscallReturn {
 #endif
 
 
-#ifdef FULL_SYSTEM
+#if FULL_SYSTEM
+//typedef TheISA::InternalProcReg InternalProcReg;
+//const int NumInternalProcRegs  = TheISA::NumInternalProcRegs;
+//const int NumInterruptLevels = TheISA::NumInterruptLevels;
 
 #include "arch/mips/mips34k.hh"
 #endif