Changes to untemplate StaticInst and StaticInstPtr, change the isa to a namespace instead of a class, an improvement to the architecture specific header file selection system, and fixed up a few include paths.

arch/alpha/alpha_linux_process.cc:
    Added using directive for AlphaISA namespace
arch/alpha/alpha_memory.hh:
arch/alpha/isa/branch.isa:
cpu/pc_event.hh:
    Added typedefs for Addr
arch/alpha/alpha_tru64_process.cc:
arch/alpha/arguments.cc:
    Added using directive for AlphaISA
arch/alpha/ev5.hh:
    Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace.
arch/alpha/faults.hh:
    Added a typedef for the Addr type, and changed the formatting of the faults slightly.
arch/alpha/isa/main.isa:
    Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh
arch/alpha/isa/mem.isa:
    Untemplatized StaticInst and StaticInstPtr
arch/alpha/isa/pal.isa:
cpu/base_dyn_inst.cc:
    Untemplatized StaticInstPtr
arch/alpha/isa_traits.hh:
    Changed variables to be externs instead of static since they are part of a namespace and not a class.
arch/alpha/stacktrace.cc:
    Untemplatized StaticInstPtr, and added a using directive for AlphaISA.
arch/alpha/stacktrace.hh:
    Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr
arch/alpha/vtophys.cc:
    Added a using directive for AlphaISA
arch/alpha/vtophys.hh:
    Added the AlphaISA namespace specifier where needed
arch/isa_parser.py:
    Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace.
base/loader/object_file.hh:
cpu/o3/bpred_unit.hh:
    Added a typedef for Addr
base/loader/symtab.hh:
    Added a typedef for Addr, and added a TheISA to Addr in another typedef
base/remote_gdb.cc:
    Added a using namespace TheISA, and untemplatized StaticInstPtr
base/remote_gdb.hh:
    Added typedefs for Addr and MachInst
cpu/base.cc:
    Added TheISA specifier to some variables exported from the isa.
cpu/base.hh:
    Added a typedef for Addr, and TheISA to some variables from the ISA
cpu/base_dyn_inst.hh:
    Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA.
cpu/exec_context.hh:
    Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa
cpu/exetrace.hh:
    Added typedefs for some types from the ISA, and untemplatized StaticInstPtr
cpu/memtest/memtest.cc:
cpu/o3/btb.cc:
dev/baddev.cc:
dev/ide_ctrl.cc:
dev/ide_disk.cc:
dev/isa_fake.cc:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/platform.cc:
dev/sinic.cc:
dev/uart8250.cc:
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
kern/system_events.cc:
kern/tru64/dump_mbuf.cc:
kern/tru64/tru64_events.cc:
sim/process.cc:
sim/pseudo_inst.cc:
sim/system.cc:
    Added using namespace TheISA
cpu/memtest/memtest.hh:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/itx_reader.hh:
dev/ide_disk.hh:
dev/pcidev.hh:
dev/platform.hh:
dev/tsunami.hh:
sim/system.hh:
sim/vptr.hh:
    Added typedef for Addr
cpu/o3/2bit_local_pred.hh:
    Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr
cpu/o3/alpha_cpu.hh:
    Added typedefs for Addr and IntReg
cpu/o3/alpha_cpu_impl.hh:
    Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed.
cpu/o3/alpha_dyn_inst.hh:
    Cleaned up some typedefs, and untemplatized StaticInst
cpu/o3/alpha_dyn_inst_impl.hh:
    untemplatized StaticInstPtr
cpu/o3/alpha_impl.hh:
    Fixed up a typedef of MachInst
cpu/o3/bpred_unit_impl.hh:
    Added a using TheISA::MachInst to a function
cpu/o3/btb.hh:
    Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr
cpu/o3/commit.hh:
    Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now.
cpu/o3/cpu.cc:
    Cleaned up namespace issues
cpu/o3/cpu.hh:
    Cleaned up namespace usage
cpu/o3/decode.hh:
    Removed typedef of ISA, and changed it to TheISA
cpu/o3/fetch.hh:
    Fized up typedefs, and changed ISA to TheISA
cpu/o3/free_list.hh:
    Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh
cpu/o3/iew.hh:
    Removed typedef of ISA
cpu/o3/iew_impl.hh:
    Added TheISA namespace specifier to MachInst
cpu/o3/ras.hh:
    Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr.
cpu/o3/regfile.hh:
    Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile
cpu/o3/rename.hh:
    Changed ISA to TheISA, and added a typedef for RegIndex
cpu/o3/rename_map.hh:
    Added an include for arch/isa_traits.hh, and a typedef for RegIndex
cpu/o3/rob.hh:
    Added a typedef for RegIndex
cpu/o3/store_set.hh:
cpu/o3/tournament_pred.hh:
    Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr
cpu/ozone/cpu.hh:
    Changed ISA into TheISA, and untemplatized StaticInst
cpu/pc_event.cc:
    Added namespace specifier TheISA to Addr types
cpu/profile.hh:
kern/kernel_stats.hh:
    Added typedef for Addr, and untemplatized StaticInstPtr
cpu/simple/cpu.cc:
    Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst
cpu/simple/cpu.hh:
    Added a typedef for MachInst, and untemplatized StaticInst
cpu/static_inst.cc:
    Untemplatized StaticInst
cpu/static_inst.hh:
    Untemplatized StaticInst by using the TheISA namespace
dev/alpha_console.cc:
    Added using namespace AlphaISA
dev/simple_disk.hh:
    Added typedef for Addr and fixed up some formatting
dev/sinicreg.hh:
    Added TheISA namespace specifier where needed
dev/tsunami.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
    Added using namespace TheISA. It might be better for it to be AlphaISA
dev/tsunami_cchip.cc:
    Added typedef for TheISA. It might be better for it to be AlphaISA
kern/linux/aligned.hh:
sim/pseudo_inst.hh:
    Added TheISA namespace specifier to Addr
kern/linux/linux_threadinfo.hh:
    Added typedef for Addr, and TheISA namespace specifier to StackPointerReg
kern/tru64/mbuf.hh:
    Added TheISA to Addr type in structs
sim/process.hh:
    Added typedefs of Addr, RegFile, and MachInst
sim/syscall_emul.cc:
    Added using namespace TheISA, and a cast of VMPageSize to the int type
sim/syscall_emul.hh:
    Added typecast for Addr, and TheISA namespace specifier for where needed

--HG--
extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45

16 files changed, 130 insertions, 95 deletions

diff --git a/arch/alpha/alpha_linux_process.cc b/arch/alpha/alpha_linux_process.cc
index fb5e32e63..af4df7c30 100644
--- a/arch/alpha/alpha_linux_process.cc
+++ b/arch/alpha/alpha_linux_process.cc
@@ -52,6 +52,7 @@
 #include "base/trace.hh"
 
 using namespace std;
+using namespace AlphaISA;
 
 ///
 /// This class encapsulates the types, structures, constants,
diff --git a/arch/alpha/alpha_memory.hh b/arch/alpha/alpha_memory.hh
index 849063f59..b39a1ef26 100644
--- a/arch/alpha/alpha_memory.hh
+++ b/arch/alpha/alpha_memory.hh
@@ -42,6 +42,7 @@ class ExecContext;
 class AlphaTLB : public SimObject
 {
   protected:
+    typedef TheISA::Addr Addr;
     typedef std::multimap<Addr, int> PageTable;
     PageTable lookupTable;	// Quick lookup into page table
 
@@ -82,6 +83,7 @@ class AlphaTLB : public SimObject
 class AlphaITB : public AlphaTLB
 {
   protected:
+    typedef TheISA::Addr Addr;
     mutable Stats::Scalar<> hits;
     mutable Stats::Scalar<> misses;
     mutable Stats::Scalar<> acv;
diff --git a/arch/alpha/alpha_tru64_process.cc b/arch/alpha/alpha_tru64_process.cc
index 5c24adad9..49e672203 100644
--- a/arch/alpha/alpha_tru64_process.cc
+++ b/arch/alpha/alpha_tru64_process.cc
@@ -55,6 +55,7 @@
 #include "sim/syscall_emul.hh"
 
 using namespace std;
+using namespace AlphaISA;
 
 typedef struct stat global_stat;
 typedef struct statfs global_statfs;
diff --git a/arch/alpha/arguments.cc b/arch/alpha/arguments.cc
index a340a2053..4e8190cbc 100644
--- a/arch/alpha/arguments.cc
+++ b/arch/alpha/arguments.cc
@@ -31,6 +31,8 @@
 #include "cpu/exec_context.hh"
 #include "mem/functional/physical.hh"
 
+using namespace AlphaISA;
+
 AlphaArguments::Data::~Data()
 {
     while (!data.empty()) {
diff --git a/arch/alpha/ev5.hh b/arch/alpha/ev5.hh
index 5173b364f..7c8465cfb 100644
--- a/arch/alpha/ev5.hh
+++ b/arch/alpha/ev5.hh
@@ -30,9 +30,13 @@
 #define __ARCH_ALPHA_EV5_HH__
 
 #include "config/alpha_tlaser.hh"
+#include "arch/alpha/isa_traits.hh"
 
 namespace EV5 {
 
+//It seems like a safe assumption EV5 only applies to alpha
+using namespace AlphaISA;
+
 #if ALPHA_TLASER
 const uint64_t AsnMask = ULL(0x7f);
 #else
diff --git a/arch/alpha/faults.hh b/arch/alpha/faults.hh
index 2bb929a1e..8c281593a 100644
--- a/arch/alpha/faults.hh
+++ b/arch/alpha/faults.hh
@@ -34,15 +34,21 @@
 
 class AlphaFault : public Fault
 {
-public:
-        AlphaFault(char * newName, int newId, Addr newVect) : Fault(newName, newId), vect(newVect) {;}
-        TheISA::Addr vect;
+  protected:
+    typedef TheISA::Addr Addr;
+  public:
+    AlphaFault(char * newName, int newId, Addr newVect) :
+        Fault(newName, newId), vect(newVect)
+    {;}
+    Addr vect;
 };
 
 extern class ResetFaultType : public AlphaFault
 {
 public:
-        ResetFaultType(char * newName, int newId, Addr newVect) : AlphaFault(newName, newId, newVect) {;}
+        ResetFaultType(char * newName, int newId, Addr newVect) :
+            AlphaFault(newName, newId, newVect)
+        {;}
 } * ResetFault;
 
 extern class ArithmeticFaultType : public AlphaFault
diff --git a/arch/alpha/isa/branch.isa b/arch/alpha/isa/branch.isa
index e9c790c53..cc6fd1a09 100644
--- a/arch/alpha/isa/branch.isa
+++ b/arch/alpha/isa/branch.isa
@@ -40,6 +40,8 @@ output header {{
     class PCDependentDisassembly : public AlphaStaticInst
     {
       protected:
+        typedef TheISA::Addr Addr;
+      protected:
         /// Cached program counter from last disassembly
         mutable Addr cachedPC;
         /// Cached symbol table pointer from last disassembly
@@ -64,6 +66,7 @@ output header {{
     class Branch : public PCDependentDisassembly
     {
       protected:
+        typedef TheISA::Addr Addr;
         /// Displacement to target address (signed).
         int32_t disp;
 
@@ -87,6 +90,7 @@ output header {{
     class Jump : public PCDependentDisassembly
     {
       protected:
+        typedef TheISA::Addr Addr;
 
         /// Displacement to target address (signed).
         int32_t disp;
@@ -205,8 +209,8 @@ output decoder {{
 
 def template JumpOrBranchDecode {{
     return (RA == 31)
-        ? (StaticInst<AlphaISA> *)new %(class_name)s(machInst)
-        : (StaticInst<AlphaISA> *)new %(class_name)sAndLink(machInst);
+        ? (StaticInst *)new %(class_name)s(machInst)
+        : (StaticInst *)new %(class_name)sAndLink(machInst);
 }};
 
 def format CondBranch(code) {{
diff --git a/arch/alpha/isa/main.isa b/arch/alpha/isa/main.isa
index 42fb29404..862b2b95e 100644
--- a/arch/alpha/isa/main.isa
+++ b/arch/alpha/isa/main.isa
@@ -45,6 +45,8 @@ output decoder {{
 #include "cpu/exec_context.hh"  // for Jump::branchTarget()
 
 #include <math.h>
+
+using namespace AlphaISA;
 }};
 
 output exec {{
@@ -58,6 +60,8 @@ output exec {{
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"
 #include "sim/sim_exit.hh"
+
+using namespace AlphaISA;
 }};
 
 ////////////////////////////////////////////////////////////////////
@@ -179,7 +183,7 @@ output header {{
     /**
      * Base class for all Alpha static instructions.
      */
-    class AlphaStaticInst : public StaticInst<AlphaISA>
+    class AlphaStaticInst : public StaticInst
     {
       protected:
 
@@ -196,7 +200,7 @@ output header {{
         /// Constructor.
         AlphaStaticInst(const char *mnem, MachInst _machInst,
                         OpClass __opClass)
-            : StaticInst<AlphaISA>(mnem, _machInst, __opClass)
+            : StaticInst(mnem, _machInst, __opClass)
         {
         }
 
@@ -352,6 +356,17 @@ output header {{
 
         %(BasicExecDeclare)s
     };
+
+    /// Helper function for decoding nops.  Substitute Nop object
+    /// for original inst passed in as arg (and delete latter).
+    static inline
+    AlphaStaticInst *
+    makeNop(AlphaStaticInst *inst)
+    {
+        AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
+        delete inst;
+        return nop;
+    }
 }};
 
 output decoder {{
@@ -364,17 +379,6 @@ output decoder {{
         return csprintf("%-10s (%s)", "nop", originalDisassembly);
 #endif
     }
-
-    /// Helper function for decoding nops.  Substitute Nop object
-    /// for original inst passed in as arg (and delete latter).
-    inline
-    AlphaStaticInst *
-    makeNop(AlphaStaticInst *inst)
-    {
-        AlphaStaticInst *nop = new Nop(inst->disassemble(0), inst->machInst);
-        delete inst;
-        return nop;
-    }
 }};
 
 output exec {{
diff --git a/arch/alpha/isa/mem.isa b/arch/alpha/isa/mem.isa
index 0b79bc376..c72806263 100644
--- a/arch/alpha/isa/mem.isa
+++ b/arch/alpha/isa/mem.isa
@@ -37,14 +37,14 @@ output header {{
         /// Memory request flags.  See mem_req_base.hh.
         unsigned memAccessFlags;
         /// Pointer to EAComp object.
-        const StaticInstPtr<AlphaISA> eaCompPtr;
+        const StaticInstPtr eaCompPtr;
         /// Pointer to MemAcc object.
-        const StaticInstPtr<AlphaISA> memAccPtr;
+        const StaticInstPtr memAccPtr;
 
         /// Constructor
         Memory(const char *mnem, MachInst _machInst, OpClass __opClass,
-               StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
-               StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
+               StaticInstPtr _eaCompPtr = nullStaticInstPtr,
+               StaticInstPtr _memAccPtr = nullStaticInstPtr)
             : AlphaStaticInst(mnem, _machInst, __opClass),
               memAccessFlags(0), eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr)
         {
@@ -55,8 +55,8 @@ output header {{
 
       public:
 
-        const StaticInstPtr<AlphaISA> &eaCompInst() const { return eaCompPtr; }
-        const StaticInstPtr<AlphaISA> &memAccInst() const { return memAccPtr; }
+        const StaticInstPtr &eaCompInst() const { return eaCompPtr; }
+        const StaticInstPtr &memAccInst() const { return memAccPtr; }
     };
 
     /**
@@ -71,8 +71,8 @@ output header {{
 
         /// Constructor.
         MemoryDisp32(const char *mnem, MachInst _machInst, OpClass __opClass,
-                     StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
-                     StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
+                     StaticInstPtr _eaCompPtr = nullStaticInstPtr,
+                     StaticInstPtr _memAccPtr = nullStaticInstPtr)
             : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
               disp(MEMDISP)
         {
@@ -90,8 +90,8 @@ output header {{
       protected:
         /// Constructor
         MemoryNoDisp(const char *mnem, MachInst _machInst, OpClass __opClass,
-                     StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
-                     StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr)
+                     StaticInstPtr _eaCompPtr = nullStaticInstPtr,
+                     StaticInstPtr _memAccPtr = nullStaticInstPtr)
             : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr)
         {
         }
diff --git a/arch/alpha/isa/pal.isa b/arch/alpha/isa/pal.isa
index b68a7c19f..49e5bff12 100644
--- a/arch/alpha/isa/pal.isa
+++ b/arch/alpha/isa/pal.isa
@@ -149,8 +149,8 @@ output header {{
 
         /// Constructor
         HwLoadStore(const char *mnem, MachInst _machInst, OpClass __opClass,
-                    StaticInstPtr<AlphaISA> _eaCompPtr = nullStaticInstPtr,
-                    StaticInstPtr<AlphaISA> _memAccPtr = nullStaticInstPtr);
+                    StaticInstPtr _eaCompPtr = nullStaticInstPtr,
+                    StaticInstPtr _memAccPtr = nullStaticInstPtr);
 
         std::string
         generateDisassembly(Addr pc, const SymbolTable *symtab) const;
@@ -162,8 +162,8 @@ output decoder {{
     inline
     HwLoadStore::HwLoadStore(const char *mnem, MachInst _machInst,
                              OpClass __opClass,
-                             StaticInstPtr<AlphaISA> _eaCompPtr,
-                             StaticInstPtr<AlphaISA> _memAccPtr)
+                             StaticInstPtr _eaCompPtr,
+                             StaticInstPtr _memAccPtr)
         : Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
         disp(HW_LDST_DISP)
     {
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index a6e34acbb..2da37b2e0 100644
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -44,17 +44,16 @@ class Checkpoint;
 
 #define TARGET_ALPHA
 
-template <class ISA> class StaticInst;
-template <class ISA> class StaticInstPtr;
+class StaticInst;
+class StaticInstPtr;
 
 namespace EV5 {
 int DTB_ASN_ASN(uint64_t reg);
 int ITB_ASN_ASN(uint64_t reg);
 }
 
-class AlphaISA
+namespace AlphaISA
 {
-  public:
 
     typedef uint32_t MachInst;
     typedef uint64_t Addr;
@@ -133,10 +132,10 @@ class AlphaISA
         Addr		lock_addr;	// lock address for LL/SC
     } MiscRegFile;
 
-static const Addr PageShift = 13;
-static const Addr PageBytes = ULL(1) << PageShift;
-static const Addr PageMask = ~(PageBytes - 1);
-static const Addr PageOffset = PageBytes - 1;
+extern const Addr PageShift;
+extern const Addr PageBytes;
+extern const Addr PageMask;
+extern const Addr PageOffset;
 
 #if FULL_SYSTEM
 
@@ -184,10 +183,10 @@ static const Addr PageOffset = PageBytes - 1;
         void unserialize(Checkpoint *cp, const std::string &section);
     };
 
-    static StaticInstPtr<AlphaISA> decodeInst(MachInst);
+    StaticInstPtr decodeInst(MachInst);
 
     // return a no-op instruction... used for instruction fetch faults
-    static const MachInst NoopMachInst;
+    extern const MachInst NoopMachInst;
 
     enum annotes {
         ANNOTE_NONE = 0,
@@ -242,10 +241,10 @@ static const Addr PageOffset = PageBytes - 1;
 
     // Machine operations
 
-    static void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
+    void saveMachineReg(AnyReg &savereg, const RegFile &reg_file,
                                int regnum);
 
-    static void restoreMachineReg(RegFile &regs, const AnyReg &reg,
+    void restoreMachineReg(RegFile &regs, const AnyReg &reg,
                                   int regnum);
 
 #if 0
@@ -263,41 +262,41 @@ static const Addr PageOffset = PageBytes - 1;
      * @param xc The execution context.
      */
     template <class XC>
-    static void zeroRegisters(XC *xc);
+    void zeroRegisters(XC *xc);
+
+
+//typedef AlphaISA TheISA;
+
+//typedef TheISA::MachInst MachInst;
+//typedef TheISA::Addr Addr;
+//typedef TheISA::RegIndex RegIndex;
+//typedef TheISA::IntReg IntReg;
+//typedef TheISA::IntRegFile IntRegFile;
+//typedef TheISA::FloatReg FloatReg;
+//typedef TheISA::FloatRegFile FloatRegFile;
+//typedef TheISA::MiscReg MiscReg;
+//typedef TheISA::MiscRegFile MiscRegFile;
+//typedef TheISA::AnyReg AnyReg;
+//typedef TheISA::RegFile RegFile;
+
+//const int NumIntRegs   = TheISA::NumIntRegs;
+//const int NumFloatRegs = TheISA::NumFloatRegs;
+//const int NumMiscRegs  = TheISA::NumMiscRegs;
+//const int TotalNumRegs = TheISA::TotalNumRegs;
+//const int VMPageSize   = TheISA::VMPageSize;
+//const int LogVMPageSize   = TheISA::LogVMPageSize;
+//const int ZeroReg = TheISA::ZeroReg;
+//const int StackPointerReg = TheISA::StackPointerReg;
+//const int GlobalPointerReg = TheISA::GlobalPointerReg;
+//const int ReturnAddressReg = TheISA::ReturnAddressReg;
+//const int ReturnValueReg = TheISA::ReturnValueReg;
+//const int ArgumentReg0 = TheISA::ArgumentReg0;
+//const int ArgumentReg1 = TheISA::ArgumentReg1;
+//const int ArgumentReg2 = TheISA::ArgumentReg2;
+//const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
+const Addr MaxAddr = (Addr)-1;
 };
 
-
-typedef AlphaISA TheISA;
-
-typedef TheISA::MachInst MachInst;
-typedef TheISA::Addr Addr;
-typedef TheISA::RegIndex RegIndex;
-typedef TheISA::IntReg IntReg;
-typedef TheISA::IntRegFile IntRegFile;
-typedef TheISA::FloatReg FloatReg;
-typedef TheISA::FloatRegFile FloatRegFile;
-typedef TheISA::MiscReg MiscReg;
-typedef TheISA::MiscRegFile MiscRegFile;
-typedef TheISA::AnyReg AnyReg;
-typedef TheISA::RegFile RegFile;
-
-const int NumIntRegs   = TheISA::NumIntRegs;
-const int NumFloatRegs = TheISA::NumFloatRegs;
-const int NumMiscRegs  = TheISA::NumMiscRegs;
-const int TotalNumRegs = TheISA::TotalNumRegs;
-const int VMPageSize   = TheISA::VMPageSize;
-const int LogVMPageSize   = TheISA::LogVMPageSize;
-const int ZeroReg = TheISA::ZeroReg;
-const int StackPointerReg = TheISA::StackPointerReg;
-const int GlobalPointerReg = TheISA::GlobalPointerReg;
-const int ReturnAddressReg = TheISA::ReturnAddressReg;
-const int ReturnValueReg = TheISA::ReturnValueReg;
-const int ArgumentReg0 = TheISA::ArgumentReg0;
-const int ArgumentReg1 = TheISA::ArgumentReg1;
-const int ArgumentReg2 = TheISA::ArgumentReg2;
-const int BranchPredAddrShiftAmt = TheISA::BranchPredAddrShiftAmt;
-const int MaxAddr = (Addr)-1;
-
 #if !FULL_SYSTEM
 class SyscallReturn {
         public:
@@ -336,9 +335,9 @@ class SyscallReturn {
 
 
 #if FULL_SYSTEM
-typedef TheISA::InternalProcReg InternalProcReg;
-const int NumInternalProcRegs  = TheISA::NumInternalProcRegs;
-const int NumInterruptLevels = TheISA::NumInterruptLevels;
+//typedef TheISA::InternalProcReg InternalProcReg;
+//const int NumInternalProcRegs  = TheISA::NumInternalProcRegs;
+//const int NumInterruptLevels = TheISA::NumInterruptLevels;
 
 #include "arch/alpha/ev5.hh"
 #endif
diff --git a/arch/alpha/stacktrace.cc b/arch/alpha/stacktrace.cc
index 5a8df3d35..30ed07d9d 100644
--- a/arch/alpha/stacktrace.cc
+++ b/arch/alpha/stacktrace.cc
@@ -37,6 +37,7 @@
 #include "cpu/exec_context.hh"
 
 using namespace std;
+using namespace AlphaISA;
 
 ProcessInfo::ProcessInfo(ExecContext *_xc)
     : xc(_xc)
@@ -108,7 +109,7 @@ StackTrace::StackTrace()
 {
 }
 
-StackTrace::StackTrace(ExecContext *_xc, StaticInstPtr<TheISA> inst)
+StackTrace::StackTrace(ExecContext *_xc, StaticInstPtr inst)
     : xc(0), stack(64)
 {
     trace(_xc, inst);
diff --git a/arch/alpha/stacktrace.hh b/arch/alpha/stacktrace.hh
index 244e574b6..211909060 100644
--- a/arch/alpha/stacktrace.hh
+++ b/arch/alpha/stacktrace.hh
@@ -37,6 +37,8 @@ class StackTrace;
 
 class ProcessInfo
 {
+  protected:
+    typedef TheISA::Addr Addr;
   private:
     ExecContext *xc;
 
@@ -56,6 +58,9 @@ class ProcessInfo
 
 class StackTrace
 {
+  protected:
+    typedef TheISA::Addr Addr;
+    typedef TheISA::MachInst MachInst;
   private:
     ExecContext *xc;
     std::vector<Addr> stack;
@@ -70,7 +75,7 @@ class StackTrace
 
   public:
     StackTrace();
-    StackTrace(ExecContext *xc, StaticInstPtr<TheISA> inst);
+    StackTrace(ExecContext *xc, StaticInstPtr inst);
     ~StackTrace();
 
     void clear()
@@ -80,7 +85,7 @@ class StackTrace
     }
 
     bool valid() const { return xc != NULL; }
-    bool trace(ExecContext *xc, StaticInstPtr<TheISA> inst);
+    bool trace(ExecContext *xc, StaticInstPtr inst);
 
   public:
     const std::vector<Addr> &getstack() const { return stack; }
@@ -102,7 +107,7 @@ class StackTrace
 };
 
 inline bool
-StackTrace::trace(ExecContext *xc, StaticInstPtr<TheISA> inst)
+StackTrace::trace(ExecContext *xc, StaticInstPtr inst)
 {
     if (!inst->isCall() && !inst->isReturn())
         return false;
diff --git a/arch/alpha/vtophys.cc b/arch/alpha/vtophys.cc
index 27014164c..3ffa4bd14 100644
--- a/arch/alpha/vtophys.cc
+++ b/arch/alpha/vtophys.cc
@@ -34,6 +34,7 @@
 #include "mem/functional/physical.hh"
 
 using namespace std;
+using namespace AlphaISA;
 
 AlphaISA::PageTableEntry
 kernel_pte_lookup(PhysicalMemory *pmem, Addr ptbr, AlphaISA::VAddr vaddr)
diff --git a/arch/alpha/vtophys.hh b/arch/alpha/vtophys.hh
index 95430ce77..988f050ba 100644
--- a/arch/alpha/vtophys.hh
+++ b/arch/alpha/vtophys.hh
@@ -35,16 +35,16 @@ class ExecContext;
 class PhysicalMemory;
 
 AlphaISA::PageTableEntry
-kernel_pte_lookup(PhysicalMemory *pmem, Addr ptbr, AlphaISA::VAddr vaddr);
+kernel_pte_lookup(PhysicalMemory *pmem, AlphaISA::Addr ptbr, AlphaISA::VAddr vaddr);
 
-Addr vtophys(PhysicalMemory *xc, Addr vaddr);
-Addr vtophys(ExecContext *xc, Addr vaddr);
-uint8_t *vtomem(ExecContext *xc, Addr vaddr, size_t len);
-uint8_t *ptomem(ExecContext *xc, Addr paddr, size_t len);
+AlphaISA::Addr vtophys(PhysicalMemory *xc, AlphaISA::Addr vaddr);
+AlphaISA::Addr vtophys(ExecContext *xc, AlphaISA::Addr vaddr);
+uint8_t *vtomem(ExecContext *xc, AlphaISA::Addr vaddr, size_t len);
+uint8_t *ptomem(ExecContext *xc, AlphaISA::Addr paddr, size_t len);
 
-void CopyOut(ExecContext *xc, void *dst, Addr src, size_t len);
-void CopyIn(ExecContext *xc, Addr dst, void *src, size_t len);
-void CopyString(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen);
+void CopyOut(ExecContext *xc, void *dst, AlphaISA::Addr src, size_t len);
+void CopyIn(ExecContext *xc, AlphaISA::Addr dst, void *src, size_t len);
+void CopyString(ExecContext *xc, char *dst, AlphaISA::Addr vaddr, size_t maxlen);
 
 #endif // __ARCH_ALPHA_VTOPHYS_H__
 
diff --git a/arch/isa_parser.py b/arch/isa_parser.py
index 96d3e8438..3fbb5276b 100755
--- a/arch/isa_parser.py
+++ b/arch/isa_parser.py
@@ -224,7 +224,7 @@ def p_specification(t):
     namespace = isa_name + "Inst"
     # wrap the decode block as a function definition
     t[4].wrap_decode_block('''
-StaticInstPtr<%(isa_name)s>
+StaticInstPtr
 %(isa_name)s::decodeInst(%(isa_name)s::MachInst machInst)
 {
     using namespace %(namespace)s;
@@ -1690,6 +1690,8 @@ namespace %(namespace)s {
 %(namespace_output)s
 
 } // namespace %(namespace)s
+
+%(decode_function)s
 '''
 
 
@@ -1769,13 +1771,15 @@ def parse_isa_desc(isa_desc_file, output_dir, include_path):
     includes = '#include "base/bitfield.hh" // for bitfield support'
     global_output = global_code.header_output
     namespace_output = namespace_code.header_output
+    decode_function = ''
     update_if_needed(output_dir + '/decoder.hh', file_template % vars())
 
     # generate decoder.cc
     includes = '#include "%s/decoder.hh"' % include_path
     global_output = global_code.decoder_output
     namespace_output = namespace_code.decoder_output
-    namespace_output += namespace_code.decode_block
+    # namespace_output += namespace_code.decode_block
+    decode_function = namespace_code.decode_block
     update_if_needed(output_dir + '/decoder.cc', file_template % vars())
 
     # generate per-cpu exec files
@@ -1784,6 +1788,7 @@ def parse_isa_desc(isa_desc_file, output_dir, include_path):
         includes += cpu.includes
         global_output = global_code.exec_output[cpu.name]
         namespace_output = namespace_code.exec_output[cpu.name]
+        decode_function = ''
         update_if_needed(output_dir + '/' + cpu.filename,
                           file_template % vars())