Clean up and fix for compilation

--HG--
extra : convert_revision : c4e66cd678313f7fe169787cb1bf3e45f114c4fd

5 files changed, 352 insertions, 355 deletions

diff --git a/arch/sparc/isa/base.isa b/arch/sparc/isa/base.isa
index f8c6ae12c..4721f728b 100644
--- a/arch/sparc/isa/base.isa
+++ b/arch/sparc/isa/base.isa
@@ -5,15 +5,19 @@
 
 output header {{
 
-        struct condCodes
+        union CondCodes
         {
-            uint8_t c:1;
-            uint8_t v:1;
-            uint8_t z:1;
-            uint8_t n:1;
+            struct
+            {
+                uint8_t c:1;
+                uint8_t v:1;
+                uint8_t z:1;
+                uint8_t n:1;
+            };
+            uint32_t bits;
         };
 
-        enum condTest
+        enum CondTest
         {
             Always=0x8,
             Never=0x0,
@@ -52,7 +56,28 @@ output header {{
             void printReg(std::ostream &os, int reg) const;
         };
 
-        bool passesCondition(condCodes codes, condTest condition);
+        bool passesCondition(uint32_t codes, uint32_t condition);
+}};
+
+def template ROrImmDecode {{
+    {
+        return (I ? (SparcStaticInst *)(new %(class_name)sImm(machInst))
+                  : (SparcStaticInst *)(new %(class_name)s(machInst)));
+    }
+}};
+
+let {{
+    def splitOutImm(code):
+        matcher = re.compile(r'Rs(?P<rNum>\d)_or_imm(?P<iNum>d{0,2})')
+        rOrImmMatch = matcher.search(code)
+        if (rOrImmMatch == None):
+            return (False, CodeBlock(code), None, '', '')
+        rString = matcher.sub(r'(?P=rNum)', rOrImmMatch.string)
+        iString = matcher.sub(r'(?P=iNum)', rOrImmMatch.string)
+        orig_code = code
+        code = matcher.sub(r'Rs(?P<rNum>)', orig_code)
+        imm_code = matcher.sub('imm', orig_code)
+        return (True, CodeBlock(code), CodeBlock(imm_code), rString, iString)
 }};
 
 output decoder {{
@@ -100,8 +125,10 @@ output decoder {{
             return ss.str();
         }
 
-        bool passesCondition(condCodes codes, condTest condition)
+        bool passesCondition(uint32_t codes, uint32_t condition)
         {
+            CondCodes condCodes;
+            condCodes.bits = codes;
             switch(condition)
             {
               case Always:
@@ -109,33 +136,33 @@ output decoder {{
               case Never:
                 return false;
               case NotEqual:
-                return !codes.z;
+                return !condCodes.z;
               case Equal:
-                return codes.z;
+                return condCodes.z;
               case Greater:
-                return !(codes.z | (codes.n ^ codes.v));
+                return !(condCodes.z | (condCodes.n ^ condCodes.v));
               case LessOrEqual:
-                return codes.z | (codes.n ^ codes.v);
+                return condCodes.z | (condCodes.n ^ condCodes.v);
               case GreaterOrEqual:
-                return !(codes.n ^ codes.v);
+                return !(condCodes.n ^ condCodes.v);
               case Less:
-                return (codes.n ^ codes.v);
+                return (condCodes.n ^ condCodes.v);
               case GreaterUnsigned:
-                return !(codes.c | codes.z);
+                return !(condCodes.c | condCodes.z);
               case LessOrEqualUnsigned:
-                return (codes.c | codes.z);
+                return (condCodes.c | condCodes.z);
               case CarryClear:
-                return !codes.c;
+                return !condCodes.c;
               case CarrySet:
-                return codes.c;
+                return condCodes.c;
               case Positive:
-                return !codes.n;
+                return !condCodes.n;
               case Negative:
-                return codes.n;
+                return condCodes.n;
               case OverflowClear:
-                return !codes.v;
+                return !condCodes.v;
               case OverflowSet:
-                return codes.v;
+                return condCodes.v;
             }
             panic("Tried testing condition nonexistant "
                     "condition code %d", condition);
diff --git a/arch/sparc/isa/decoder.isa b/arch/sparc/isa/decoder.isa
index 14280ef12..eda11d7a5 100644
--- a/arch/sparc/isa/decoder.isa
+++ b/arch/sparc/isa/decoder.isa
@@ -7,186 +7,127 @@ decode OP default Unknown::unknown()
 {
     0x0: decode OP2
     {
-        //Throw an illegal instruction acception
-        0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
-        0x1: Branch::bpcc({{
-            switch((CC12 << 1) | CC02)
+        format Branch
+        {
+            //Throw an illegal instruction acception
+            0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
+            0x1: decode CC02
             {
-              case 1:
-              case 3:
-                fault = new IllegalInstruction;
-              case 0:
+                0x0: decode CC12
+                {
+                    0x0: bpcci({{
+                        if(passesCondition(CcrIcc, COND2))
+                            ;//branchHere
+                    }});
+                    0x1: bpccx({{
+                    if(passesCondition(CcrXcc, COND2))
+                        ;//branchHere
+                    }});
+                }
+            }
+            0x2: bicc({{
                 if(passesCondition(CcrIcc, COND2))
                     ;//branchHere
-                break;
-              case 2:
-                if(passesCondition(CcrXcc, COND2))
-                    ;//branchHere
-                break;
-            }
-        }});//BPcc
-        0x2: Branch::bicc({{
-            if(passesCondition(CcrIcc, COND2))
-                ;//branchHere
-        }});//Bicc
-        0x3: Branch::bpr({{
-            switch(RCOND2)
+            }});
+            0x3: decode RCOND2
             {
-              case 0:
-              case 4:
-                fault = new IllegalInstruction;
-              case 1:
-                if(Rs1 == 0)
-                    ;//branchHere
-                break;
-              case 2:
-                if(Rs1 <= 0)
-                    ;//branchHere
-                break;
-              case 3:
-                if(Rs1 < 0)
-                    ;//branchHere
-                break;
-              case 5:
-                if(Rs1 != 0)
-                    ;//branchHere
-                break;
-              case 6:
-                if(Rs1 > 0)
-                    ;//branchHere
-                break;
-              case 7:
-                if(Rs1 >= 0)
-                    ;//branchHere
-                break;
+                0x1: bpreq({{
+                    if(Rs1 == 0)
+                        ;//branchHere
+                }});
+                0x2: bprle({{
+                    if(Rs1 <= 0)
+                        ;//branchHere
+                }});
+                0x3: bprl({{
+                    if(Rs1 < 0)
+                        ;//branchHere
+                }});
+                0x5: bprne({{
+                    if(Rs1 != 0)
+                        ;//branchHere
+                }});
+                0x6: bprg({{
+                    if(Rs1 > 0)
+                        ;//branchHere
+                }});
+                0x7: bprge({{
+                    if(Rs1 >= 0)
+                        ;//branchHere
+                }});
             }
-            }});    //BPr
             //SETHI (or NOP if rd == 0 and imm == 0)
-            0x4: IntegerOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}});
+            0x4: IntOp::sethi({{Rd = (IMM22 << 10) & 0xFFFFFC00;}});
             0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
             0x6: Trap::fbfcc({{fault = new FpDisabled;}});
+        }
     }
     0x1: Branch::call({{
             //branch here
-            Rd = xc->pc;
+            Rd = xc->readPC();
     }});
     0x2: decode OP3 {
-        format IntegerOp {
-            0x00: add({{
-                int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                Rd = Rs1.sdw + val2;
-            }});//ADD
-            0x01: and({{
-                uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
-                Rd = Rs1.udw & val2;
-            }});//AND
-            0x02: or({{
-                uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
-                Rd = Rs1.udw | val2;
-            }});//OR
-            0x03: xor({{
-                uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
-                Rd = Rs1.udw ^ val2;
-            }});//XOR
-            0x04: sub({{
-                int64_t val2 = ~((uint64_t)(I ? SIMM13.sdw : Rs2.udw))+1;
-                Rd = Rs1.sdw + val2;
-            }});//SUB
-            0x05: andn({{
-                uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
-                Rd = Rs1.udw & ~val2;
-            }});//ANDN
-            0x06: orn({{
-                uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
-                Rd = Rs1.udw | ~val2;
-            }});//ORN
-            0x07: xnor({{
-                uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
-                Rd = ~(Rs1.udw ^ val2);
-            }});//XNOR
-            0x08: addc({{
-                int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                int64_t carryin = CcrIccC;
-                Rd = Rs1.sdw + val2 + carryin;
-            }});//ADDC
-            0x09: mulx({{
-                int64_t val2 = (I ? SIMM13.sdw : Rs2);
-                Rd = Rs1 * val2;
-            }});//MULX
+        format IntOp {
+            0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
+            0x01: and({{Rd = Rs1.udw & Rs2_or_imm13;}});
+            0x02: or({{Rd = Rs1.udw | Rs2_or_imm13;}});
+            0x03: xor({{Rd = Rs1.udw ^ Rs2_or_imm13;}});
+            0x04: sub({{Rd = Rs1.sdw + (~Rs2_or_imm)+1;}});
+            0x05: andn({{Rd = Rs1.udw & ~Rs2_or_imm;}});
+            0x06: orn({{Rd = Rs1.udw | ~Rs2_or_imm;}});
+            0x07: xnor({{Rd = ~(Rs1.udw ^ Rs2_or_imm);}});
+            0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm + CcrIccC;}});
+            0x09: mulx({{Rd = Rs1 * Rs2_or_imm;}});
             0x0A: umul({{
-                uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.udw);
-                Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
-                YValue = resTemp<63:32>;
-            }});//UMUL
+                Rd = Rs1.udw<31:0> * Rs2_or_imm<31:0>;
+                YValue = Rd<63:32>;
+            }});
             0x0B: smul({{
-                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                rd.sdw = resTemp = Rs1.sdw<31:0> * val2<31:0>;
-                YValue = resTemp<63:32>;
-            }});//SMUL
-            0x0C: subc({{
-                int64_t val2 = ~((int64_t)(I ? SIMM13.sdw : Rs2.sdw))+1;
-                int64_t carryin = CcrIccC;
-                Rd.sdw = Rs1.sdw + val2 + carryin;
-            }});//SUBC
+                Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm<31:0>;
+                YValue = Rd.sdw;
+            }});
+            0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm) + 1 + CcrIccC;}});
             0x0D: udivx({{
-                uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
                 if(val2 == 0) fault = new DivisionByZero;
-                else Rd.udw = Rs1.udw / val2;
-            }});//UDIVX
+                else Rd.udw = Rs1.udw / Rs2_or_imm;
+            }});
             0x0E: udiv({{
-                uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
-                if(val2 == 0)
-                    fault = new DivisionByZero;
-                resTemp = (uint64_t)((YValue << 32)
-                    | Rs1.udw<31:0>) / val2;
-                int32_t overflow = (resTemp<63:32> != 0);
-                if(overflow)
-                    rd.udw = resTemp = 0xFFFFFFFF;
+                uint32_t resTemp, val2 = (I ? SIMM13 : Rs2.udw<31:0>);
+                if(Rs2_or_imm.udw == 0) fault = new DivisionByZero;
                 else
-                    rd.udw = resTemp;
-            }});   //UDIV
+                {
+                    Rd.udw = ((YValue << 32) | Rs1.udw<31:0>) / Rs2_or_imm.udw;
+                    if(Rd.udw >> 32 != 0)
+                        Rd.udw = 0xFFFFFFFF;
+                }
+            }});
             0x0F: sdiv({{
-                int32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
                 if(val2 == 0)
                     fault = new DivisionByZero;
-
-                Rd.sdw = (int64_t)((YValue << 32) |
-                    Rs1.sdw<31:0>) / val2;
-                resTemp = Rd.sdw;
-                int32_t overflow = (resTemp<63:31> != 0);
-                int32_t underflow =
-                    (resTemp<63:> && resTemp<62:31> != 0xFFFFFFFF);
-                if(overflow)
-                    rd.udw = resTemp = 0x7FFFFFFF;
-                else if(underflow)
-                    rd.udw = resTemp = 0xFFFFFFFF80000000;
                 else
-                    rd.udw = resTemp;
+                {
+                    Rd.udw = ((YValue << 32) | Rs1.sdw<31:0>) / Rs2_or_imm;
+                    if(Rd.udw<63:31> != 0)
+                        Rd.udw = 0x7FFFFFFF;
+                    else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
+                        Rd.udw = 0xFFFFFFFF80000000;
+                }
             }});//SDIV
         }
-        format IntegerOpCc {
+        format IntOpCc {
             0x10: addcc({{
-                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
+                int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
                 Rd = resTemp = Rs1 + val2;}},
                 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
                 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
                 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
                 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
                 );//ADDcc
-            0x11: andcc({{
-                int64_t val2 = (I ? SIMM13.sdw : Rs2);
-                Rd = Rs1 & val2;}},
-                {{0}},{{0}},{{0}},{{0}});//ANDcc
-            0x12: orcc({{
-                int64_t val2 = (I ? SIMM13.sdw : Rs2);
-                Rd = Rs1 | val2;}},
-                {{0}},{{0}},{{0}},{{0}});//ORcc
-            0x13: xorcc({{
-                int64_t val2 = (I ? SIMM13.sdw : Rs2);
-                Rd = Rs1 ^ val2;}},
-                {{0}},{{0}},{{0}},{{0}});//XORcc
+            0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
+            0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
+            0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
             0x14: subcc({{
-                int64_t resTemp, val2 = (int64_t)(I ? SIMM13.sdw : Rs2);
+                int64_t resTemp, val2 = (int64_t)(I ? SIMM13 : Rs2);
                 Rd = resTemp = Rs1 - val2;}},
                 {{((Rs1 & 0xFFFFFFFF + (~val2) & 0xFFFFFFFF + 1) >> 31)}},
                 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
@@ -194,20 +135,11 @@ decode OP default Unknown::unknown()
                     ((Rs1 | ~val2) & 0x1))<63:>}},
                 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
             );//SUBcc
-            0x15: andncc({{
-                int64_t val2 = (I ? SIMM13.sdw : Rs2);
-                Rd = Rs1 & ~val2;}},
-                {{0}},{{0}},{{0}},{{0}});//ANDNcc
-            0x16: orncc({{
-                int64_t val2 = (I ? SIMM13.sdw : Rs2);
-                Rd = Rs1 | ~val2;}},
-                {{0}},{{0}},{{0}},{{0}});//ORNcc
-            0x17: xnorcc({{
-                int64_t val2 = (I ? SIMM13.sdw : Rs2);
-                Rd = ~(Rs1 ^ val2);}},
-                {{0}},{{0}},{{0}},{{0}});//XNORcc
+            0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
+            0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
+            0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
             0x18: addccc({{
-                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
+                int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
                 int64_t carryin = CcrIccC;
                 Rd = resTemp = Rs1 + val2 + carryin;}},
                 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31
@@ -218,17 +150,17 @@ decode OP default Unknown::unknown()
                 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
             );//ADDCcc
             0x1A: umulcc({{
-                uint64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
+                uint64_t resTemp, val2 = (I ? SIMM13 : Rs2);
                 Rd = resTemp = Rs1.udw<31:0> * val2<31:0>;
                 YValue = resTemp<63:32>;}},
                 {{0}},{{0}},{{0}},{{0}});//UMULcc
             0x1B: smulcc({{
-                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
+                int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
                 Rd = resTemp = Rs1.sdw<31:0> * val2<31:0>;
                 YValue = resTemp<63:32>;}}
                 ,{{0}},{{0}},{{0}},{{0}});//SMULcc
             0x1C: subccc({{
-                int64_t resTemp, val2 = (int64_t)(I ? SIMM13.sdw : Rs2);
+                int64_t resTemp, val2 = (int64_t)(I ? SIMM13 : Rs2);
                 int64_t carryin = CcrIccC;
                 Rd = resTemp = Rs1 + ~(val2 + carryin) + 1;}},
                 {{((Rs1 & 0xFFFFFFFF + (~(val2 + carryin)) & 0xFFFFFFFF + 1) >> 31)}},
@@ -237,12 +169,12 @@ decode OP default Unknown::unknown()
                 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
             );//SUBCcc
             0x1D: udivxcc({{
-                uint64_t val2 = (I ? SIMM13.sdw : Rs2.udw);
+                uint64_t val2 = (I ? SIMM13 : Rs2.udw);
                 if(val2 == 0) fault = new DivisionByZero;
                 else Rd.udw = Rs1.udw / val2;}}
                 ,{{0}},{{0}},{{0}},{{0}});//UDIVXcc
             0x1E: udivcc({{
-                uint32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.udw<31:0>);
+                uint32_t resTemp, val2 = (I ? SIMM13 : Rs2.udw<31:0>);
                 if(val2 == 0) fault = new DivisionByZero;
                 else
                 {
@@ -257,7 +189,7 @@ decode OP default Unknown::unknown()
                 {{0}}
             );//UDIVcc
             0x1F: sdivcc({{
-                int32_t resTemp, val2 = (I ? SIMM13.sw : Rs2.sdw<31:0>);
+                int32_t resTemp, val2 = (I ? SIMM13 : Rs2.sdw<31:0>);
                 if(val2 == 0) fault = new DivisionByZero;
                 else
                 {
@@ -274,7 +206,7 @@ decode OP default Unknown::unknown()
                 {{0}}
             );//SDIVcc
             0x20: taddcc({{
-                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
+                int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
                 Rd = resTemp = Rs1 + val2;
                 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
                 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
@@ -283,7 +215,7 @@ decode OP default Unknown::unknown()
                 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
             );//TADDcc
             0x21: tsubcc({{
-                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
+                int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
                 Rd = resTemp = Rs1 + val2;
                 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
                 {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
@@ -292,7 +224,7 @@ decode OP default Unknown::unknown()
                 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
             );//TSUBcc
             0x22: taddcctv({{
-                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
+                int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
                 Rd = resTemp = Rs1 + val2;
                 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
                 if(overflow) fault = new TagOverflow;}},
@@ -302,7 +234,7 @@ decode OP default Unknown::unknown()
                 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
             );//TADDccTV
             0x23: tsubcctv({{
-                int64_t resTemp, val2 = (I ? SIMM13.sdw : Rs2);
+                int64_t resTemp, val2 = (I ? SIMM13 : Rs2);
                 Rd = resTemp = Rs1 + val2;
                 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
                 if(overflow) fault = new TagOverflow;}},
@@ -312,7 +244,7 @@ decode OP default Unknown::unknown()
                 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
             );//TSUBccTV
             0x24: mulscc({{
-                int64_t resTemp, multiplicand = (I ? SIMM13.sdw : Rs2);
+                int64_t resTemp, multiplicand = (I ? SIMM13 : Rs2);
                 int32_t multiplier = Rs1<31:0>;
                 int32_t savedLSB = Rs1<0:>;
                 multiplier = multipler<31:1> |
@@ -328,46 +260,46 @@ decode OP default Unknown::unknown()
                 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
             );//MULScc
             }
-            format IntegerOp
+            format IntOp
             {
                 0x25: decode X {
-                        0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}}); //SLL
-                        0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}}); //SLLX
+                    0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
+                    0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
                 }
                 0x26: decode X {
-                        0x0: srl({{Rd = Rs1.udw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRL
-                        0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRLX
+                    0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
+                    0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
                 }
                 0x27: decode X {
-                        0x0: sra({{Rd = Rs1.sdw<31:0> >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRA
-                        0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRAX
+                    0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}}); //SRA
+                    0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});//SRAX
                 }
                 0x28: decode RS1 {
-                        0x0: rdy({{Rd = YValue;}}); //RDY
-                        0x2: rdccr({{Rd = Ccr;}}); //RDCCR
-                        0x3: rdasi({{Rd = Asi;}}); //RDASI
-                        0x4: PrivTick::rdtick({{Rd = Tick;}});
-                        0x5: rdpc({{Rd = xc->regs.pc;}}); //RDPC
-                        0x6: rdfprs({{Rd = Fprs;}}); //RDFPRS
-                        0xF: decode I {
-                            0x0: Noop::membar({{//Membar isn't needed yet}});
-                            0x1: Noop::stbar({{//Stbar isn't needed yet}});
-                        }
+                    0x0: rdy({{Rd = YValue;}}); //RDY
+                    0x2: rdccr({{Rd = Ccr;}}); //RDCCR
+                    0x3: rdasi({{Rd = Asi;}}); //RDASI
+                    0x4: PrivTick::rdtick({{Rd = Tick;}});
+                    0x5: rdpc({{Rd = xc->regs.pc;}}); //RDPC
+                    0x6: rdfprs({{Rd = Fprs;}}); //RDFPRS
+                    0xF: decode I {
+                        0x0: Noop::membar({{//Membar isn't needed yet}});
+                        0x1: Noop::stbar({{//Stbar isn't needed yet}});
+                    }
                 }
                 0x2A: decode RS1 {
                     format Priv
                     {
                         0x0: rdprtpc({{
-                            Rd = xc->readMiscReg(MISCREG_TPC_BASE + tl);
+                            Rd = xc->readMiscReg(MISCREG_TPC_BASE + Tl);
                             }});
                         0x1: rdprtnpc({{
-                            Rd = xc->readMiscReg(MISCREG_TNPC_BASE + tl);
+                            Rd = xc->readMiscReg(MISCREG_TNPC_BASE + Tl);
                             }});
                         0x2: rdprtstate({{
-                            Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + tl);
+                            Rd = xc->readMiscReg(MISCREG_TSTATE_BASE + Tl);
                             }});
                         0x3: rdprtt({{
-                            Rd = xc->readMiscReg(MISCREG_TT_BASE + tl);
+                            Rd = xc->readMiscReg(MISCREG_TT_BASE + Tl);
                             }});
                         0x4: rdprtick({{Rd = Tick;}});
                         0x5: rdprtba({{Rd = Tba;}});
@@ -385,110 +317,77 @@ decode OP default Unknown::unknown()
                     0xF: Trap::rdprfq({{fault = IllegalInstruction;}});
                     0x1F: Priv::rdprver({{Rd = Ver;}});
                 }
-                0x2B: BasicOperate::flushw({{\\window toilet}}); //FLUSHW
-                0x2C: movcc({{
-                        ccBank = (CC24 << 2) | (CC14 << 1) | (CC04 << 0);
-                        switch(ccBank)
+                0x2B: BasicOperate::flushw({{//window toilet}}); //FLUSHW
+                0x2C: decode CC2
+                {
+                    0x0: Trap::movccfcc({{fault = new FpDisabled}});
+                    0x1: decode CC04
+                    {
+                        0x0: decode CC14
                         {
-                                case 0: case 1: case 2: case 3:
-                                        fault = new FpDisabled;
-                                break;
-                                case 5: case 7:
-                                        fault = new IllegalInstruction;
-                                break;
-                                case 4:
-                                        if(passesCondition(CcrIcc, COND4))
-                                                Rd = (I ? SIMM11.sdw : RS2);
-                                break;
-                                case 6:
-                                        if(passesCondition(CcrXcc, COND4))
-                                                Rd = (I ? SIMM11.sdw : RS2);
-                                break;
+                            0x0: movcci({{
+                                if(passesCondition(CcrIcc, COND4))
+                                    Rd = (I ? SIMM11 : RS2);
+                            }});
+                            0x1: movccx({{
+                                if(passesCondition(CcrXcc, COND4))
+                                    Rd = (I ? SIMM11 : RS2);
+                            }});
                         }
-                }});//MOVcc
+                    }
+                }
                 0x2D: sdivx({{
-                        int64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                        if(val2 == 0) fault = new DivisionByZero;
-                        else Rd.sdw = Rs1.sdw / val2;
+                        if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
+                        else Rd.sdw = Rs1.sdw / Rs2_or_imm13;
                 }});//SDIVX
                 0x2E: decode RS1 {
-                        0x0: IntegerOp::popc({{
-                        int64_t count = 0, val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                        uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4}
+                        0x0: IntOp::popc({{
+                        int64_t count = 0, val2 = Rs2_or_imm;
+                        uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
                         for(unsigned int x = 0; x < 16; x++)
                         {
-                                count += oneBits[val2 & 0xF];
+                                count += oneBits[Rs2_or_imm13 & 0xF];
                                 val2 >> 4;
                         }
                         }});//POPC
                 }
-                0x2F: movr({{
-                        uint64_t val2 = (I ? SIMM10.sdw : Rs2.sdw);
-                        switch(RCOND3)
-                        {
-                                case 0: case 4:
-                                        fault = IllegalInstruction;
-                                break;
-                                case 1:
-                                        if(Rs1 == 0) Rd = val2;
-                                break;
-                                case 2:
-                                        if(Rs1 <= 0) Rd = val2;
-                                break;
-                                case 3:
-                                        if(Rs1 = 0) Rd = val2;
-                                break;
-                                case 5:
-                                        if(Rs1 != 0) Rd = val2;
-                                break;
-                                case 6:
-                                        if(Rs1 > 0) Rd = val2;
-                                break;
-                                case 7:
-                                        if(Rs1 >= 0) Rd = val2;
-                                break;
-                        }
-                }});//MOVR
+                0x2F: decode RCOND3
+                {
+                    0x1: movreq({{if(Rs1 == 0) Rd = Rs2_or_imm10;}});
+                    0x2: movrle({{if(Rs1 <= 0) Rd = Rs2_or_imm10;}});
+                    0x3: movrl({{if(Rs1 < 0) Rd = Rs2_or_imm10;}});
+                    0x5: movrne({{if(Rs1 != 0) Rd = Rs2_or_imm10;}});
+                    0x6: movrg({{if(Rs1 > 0) Rd = Rs2_or_imm10;}});
+                    0x7: movrge({{if(Rs1 >= 0) Rd = Rs2_or_imm10;}});
+                }
                 0x30: decode RD {
-                        0x0: wry({{
-                                uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                Y = Rs1 ^ val2;
-                        }});//WRY
-                        0x2: wrccr({{
-                                uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                Ccr = Rs1 ^ val2;
-                        }});//WRCCR
-                        0x3: wrasi({{
-                                uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                Asi = Rs1 ^ val2;
-                        }});//WRASI
-                        0x6: wrfprs({{
-                                uint64_t val2 = (I ? SIMM13.sdw : Rs2.sdw);
-                                Asi = Rs1 ^ val2;
-                        }});//WRFPRS
+                        0x0: wry({{Y = Rs1 ^ Rs2_or_imm13;}});
+                        0x2: wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
+                        0x3: wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
+                        0x6: wrfprs({{Asi = Rs1 ^ Rs2_or_imm13;}});
                         0xF: Trap::sir({{fault = new SoftwareInitiatedReset;}});
                 }
                 0x31: decode FCN {
-                        0x0: BasicOperate::saved({{\\Boogy Boogy}}); //SAVED
-                        0x1: BasicOperate::restored({{\\Boogy Boogy}}); //RESTORED
+                        0x0: BasicOperate::saved({{//Boogy Boogy}}); //SAVED
+                        0x1: BasicOperate::restored({{//Boogy Boogy}}); //RESTORED
                 }
                 0x32: decode RD {
                     format Priv
                     {
                         0x0: wrprtpc({{
-                            xc->setMiscReg(MISCREG_TPC_BASE + tl,
+                            xc->setMiscReg(MISCREG_TPC_BASE + Tl,
                                 Rs1 ^ Rs2_or_imm13);
                         }});
                         0x1: wrprtnpc({{
-                            xc->setMiscReg(MISCREG_TNPC_BASE + tl,
+                            xc->setMiscReg(MISCREG_TNPC_BASE + Tl,
                                 Rs1 ^ Rs2_or_imm13);
                         }});
                         0x2: wrprtstate({{
-                            xc->setMiscReg(MISCREG_TSTATE_BASE + tl,
+                            xc->setMiscReg(MISCREG_TSTATE_BASE + Tl,
                                 Rs1 ^ Rs2_or_imm13);
                         }});
                         0x3: wrprtt({{
-                            xc->setMiscReg(MISCREG_TT_BASE + tl,
+                            xc->setMiscReg(MISCREG_TT_BASE + Tl,
                                 Rs1 ^ Rs2_or_imm13);
                         }});
                         0x4: wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
@@ -508,7 +407,6 @@ decode OP default Unknown::unknown()
                 0x34: Trap::fpop1({{fault = new FpDisabled;}});
                 0x35: Trap::fpop2({{fault = new FpDisabled;}});
 
-
                 0x38: Branch::jmpl({{//Stuff}}); //JMPL
                 0x39: Branch::return({{//Other Stuff}}); //RETURN
                 0x3A: decode CC04
@@ -517,11 +415,11 @@ decode OP default Unknown::unknown()
                     0x0: decode CC14
                     {
                         0x0: Trap::tcci({{
-                            if(passesCondition(ccr_icc, machInst<25:28>))
+                            if(passesCondition(CcrIcc, machInst<25:28>))
                                 fault = new TrapInstruction;
                         }});
                         0x1: Trap::tccx({{
-                            if(passesCondition(ccr_xcc, machInst<25:28>))
+                            if(passesCondition(CcrXcc, machInst<25:28>))
                                 fault = new TrapInstruction;
                         }});
                     }
@@ -530,8 +428,8 @@ decode OP default Unknown::unknown()
                 0x3C: BasicOperate::save({{//leprechauns); //SAVE
                 0x3D: BasicOperate::restore({{//Eat my short int}}); //RESTORE
                 0x3E: decode FCN {
-                        0x1: BasicOperate::done({{//Done thing}}); //DONE
-                        0x2: BasicOperate::retry({{//Retry thing}}); //RETRY
+                    0x1: BasicOperate::done({{//Done thing}}); //DONE
+                    0x2: BasicOperate::retry({{//Retry thing}}); //RETRY
                 }
             }
     }
@@ -541,9 +439,9 @@ decode OP default Unknown::unknown()
                     0x01: ldub({{Rd.ub = Mem.ub;}}); //LDUB
                     0x02: lduh({{Rd.uhw = Mem.uhw;}}); //LDUH
                     0x03: ldd({{
-                            uint64_t val = Mem.udw;
-                            setIntReg(RD & (~1), val<31:0>);
-                            setIntReg(RD | 1, val<63:32>);
+                        uint64_t val = Mem.udw;
+                        setIntReg(RD & (~1), val<31:0>);
+                        setIntReg(RD | 1, val<63:32>);
                     }});//LDD
                     0x04: stw({{Mem.sw = Rd.sw;}}); //STW
                     0x05: stb({{Mem.sb = Rd.sb;}}); //STB
@@ -627,8 +525,8 @@ decode OP default Unknown::unknown()
                             Rd.uw = val;
                     }}); //CASA
                     0x3D: Noop::prefetcha({{ }}); //PREFETCHA
-                    0x3E: Cas::casxa(
-                            {{uint64_t val = Mem.udw;
+                    0x3E: Cas::casxa({{
+                            uint64_t val = Mem.udw;
                             if(Rs2 == val)
                                     Mem.udw = Rd;
                             Rd = val;
diff --git a/arch/sparc/isa/formats/integerop.isa b/arch/sparc/isa/formats/integerop.isa
index 7b6bfa54d..e7bd4c2a4 100644
--- a/arch/sparc/isa/formats/integerop.isa
+++ b/arch/sparc/isa/formats/integerop.isa
@@ -7,11 +7,11 @@ output header {{
         /**
          * Base class for integer operations.
          */
-        class IntegerOp : public SparcStaticInst
+        class IntOp : public SparcStaticInst
         {
           protected:
             // Constructor
-            IntegerOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
+            IntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
                 SparcStaticInst(mnem, _machInst, __opClass)
             {
             }
@@ -19,24 +19,68 @@ output header {{
             std::string generateDisassembly(Addr pc,
                 const SymbolTable *symtab) const;
         };
+
+        /**
+         * Base class for 10 bit immediate integer operations.
+         */
+        class IntOpImm10 : public IntOp
+        {
+          protected:
+            // Constructor
+            IntOpImm10(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
+                IntOp(mnem, _machInst, __opClass), imm(SIMM10)
+            {
+            }
+
+            uint32_t imm;
+        };
+
+        /**
+         * Base class for 13 bit immediate integer operations.
+         */
+        class IntOpImm13 : public IntOp
+        {
+          protected:
+            // Constructor
+            IntOpImm13(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
+                IntOp(mnem, _machInst, __opClass), imm(SIMM13)
+            {
+            }
+
+            uint32_t imm;
+        };
 }};
 
 output decoder {{
-        std::string IntegerOp::generateDisassembly(Addr pc,
+        std::string IntOp::generateDisassembly(Addr pc,
                 const SymbolTable *symtab) const
         {
             return "Integer instruction\n";
         }
 }};
 
-def template IntegerExecute {{
+def template IntOpExecute {{
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+                Trace::InstRecord *traceData) const
+        {
+            Fault fault = NoFault;
+
+            %(op_decl)s;
+            %(op_rd)s;
+            %(code)s;
+
+            //Write the resulting state to the execution context
+            if(fault == NoFault)
+                %(op_wb)s;
+            return fault;
+        }
+}};
+
+def template IntOpCcExecute {{
         Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                 Trace::InstRecord *traceData) const
         {
             Fault fault;
-            //These are set to constants when the execute method
-            //is generated
-            bool useCc = ;
 
             %(op_decl)s;
             %(op_rd)s;
@@ -46,46 +90,76 @@ def template IntegerExecute {{
             if(fault == NoFault)
             {
                 %(op_wb)s;
-                if(useCc)
-                {
-                    CcrIccN = Rd & (1 << 63);
-                    CcrIccZ = (Rd == 0);
-                    CcrIccV = ivValue;
-                    CcrIccC = icValue;
-                    CcrXccN = Rd & (1 << 31);
-                    CcrXccZ = ((Rd & 0xFFFFFFFF) == 0);
-                    CcrXccV = xvValue;
-                    CcrXccC = xcValue;
-                }
+                CcrIccN = Rd & (1 << 63);
+                CcrIccZ = (Rd == 0);
+                CcrIccV = ivValue;
+                CcrIccC = icValue;
+                CcrXccN = Rd & (1 << 31);
+                CcrXccZ = ((Rd & 0xFFFFFFFF) == 0);
+                CcrXccV = xvValue;
+                CcrXccC = xcValue;
             }
             return fault;
         }
 }};
 
-// Primary format for integer operate instructions:
-def format IntegerOp(code, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        for (marker, value) in (('ivValue', '0'), ('icValue', '0'),
-                       ('xvValue', '0'), ('xcValue', '0')):
-                code.replace(marker, value)
-        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
+def template IntOpCcResExecute {{
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
+                Trace::InstRecord *traceData) const
+        {
+            Fault fault;
+
+            %(op_decl)s;
+            %(op_rd)s;
+            %(code)s;
+
+            //Write the resulting state to the execution context
+            if(fault == NoFault)
+            {
+                %(op_wb)s;
+                CcrIccN = Rd & (1 << 63);
+                CcrIccZ = (Rd == 0);
+                CcrXccN = Rd & (1 << 31);
+                CcrXccZ = ((Rd & 0xFFFFFFFF) == 0);
+                CcrIccV = CcrIccC = CcrXccV = CcrXccC = 0;
+            }
+            return fault;
+        }
+}};
+
+let {{
+    def doIntFormat(code, execTemplate, name, Name, opt_flags):
+        (usesImm, cblk, immCblk, rString, iString) = splitOutImm(code)
+        iop = InstObjParams(name, Name, 'IntOp', cblk, opt_flags)
         header_output = BasicDeclare.subst(iop)
         decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecode.subst(iop)
-        exec_output = IntegerExecute.subst(iop)
+        exec_output = execTemplate.subst(iop)
+        if usesImm:
+            imm_iop = InstObjParams(name, Name + 'Imm', 'IntOpImm' + iString,
+                    immCblk, opt_flags)
+            header_output += BasicDeclare.subst(imm_iop)
+            decoder_output += BasicConstructor.subst(imm_iop)
+            exec_output += execTemplate.subst(imm_iop)
+            decode_block = ROrImmDecode.subst(iop)
+        else:
+            decode_block = BasicDecode.subst(iop)
 }};
 
 // Primary format for integer operate instructions:
-def format IntegerOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
-        orig_code = code
-        cblk = CodeBlock(code)
-        for (marker, value) in (('ivValue', ivValue), ('icValue', icValue),
-                       ('xvValue', xvValue), ('xcValue', xcValue)):
-                code.replace(marker, value)
-        iop = InstObjParams(name, Name, 'SparcStaticInst', cblk, opt_flags)
-        header_output = BasicDeclare.subst(iop)
-        decoder_output = BasicConstructor.subst(iop)
-        decode_block = BasicDecode.subst(iop)
-        exec_output = IntegerExecute.subst(iop)
+def format IntOp(code, *opt_flags) {{
+    doIntFormat(code, IntOpExecute, name, Name, opt_flags)
 }};
+
+// Primary format for integer operate instructions:
+def format IntOpCc(code, icValue, ivValue, xcValue, xvValue, *opt_flags) {{
+    for (marker, value) in (('ivValue', ivValue), ('icValue', icValue),
+                   ('xvValue', xvValue), ('xcValue', xcValue)):
+            code.replace(marker, value)
+    doIntFormat(code, IntOpCcExecute, name, Name, opt_flags)
+}};
+
+// Primary format for integer operate instructions:
+def format IntOpCcRes(code, *opt_flags) {{
+    doIntFormat(code, IntOpCcResExecute, name, Name, opt_flags)
+}};
+
diff --git a/arch/sparc/isa/formats/priv.isa b/arch/sparc/isa/formats/priv.isa
index 7c0d8a985..c89e769b4 100644
--- a/arch/sparc/isa/formats/priv.isa
+++ b/arch/sparc/isa/formats/priv.isa
@@ -1,6 +1,6 @@
 ////////////////////////////////////////////////////////////////////
 //
-// Privelege mode instructions
+// Privilege mode instructions
 //
 
 output header {{
@@ -92,8 +92,8 @@ def template PrivExecute {{
         %(op_rd)s;
 
         //If the processor isn't in privileged mode, fault out right away
-        if(!pstate_priv)
-            return new PrivilegedOpCode
+        if(!PstatePriv)
+            return new PrivilegedOpcode
 
         %(code)s;
         %(op_wb)s;
@@ -108,7 +108,7 @@ def template PrivTickExecute {{
         %(op_rd)s;
 
         //If the processor isn't in privileged mode, fault out right away
-        if(!pstate_priv && tick_npt)
+        if(!PstatePriv && TickNpt)
             return new PrivilegedAction
 
         %(code)s;
@@ -116,20 +116,13 @@ def template PrivTickExecute {{
     }
 }};
 
-def template Rb2OrImm13Decode {{
-    {
-        return (I ? (SparcStaticInst *)(new %(class_name)sImm(machInst))
-                  : (SparcStaticInst *)(new %(class_name)s(machInst)));
-    }
-}};
-
 // Primary format for integer operate instructions:
 def format Priv(code, *opt_flags) {{
         uses_imm = (code.find('Rs2_or_imm13') != -1)
         if uses_imm:
             orig_code = code
-            code = re.sub(r'Rs2_or_imm', 'Rs2', orig_code)
-            imm_code = re.sub(r'Rs2_or_imm(\.\w+)?', 'imm', orig_code)
+            code = re.sub(r'Rs2_or_imm13', 'Rs2', orig_code)
+            imm_code = re.sub(r'Rs2_or_imm13(\.\w+)?', 'imm', orig_code)
         cblk = CodeBlock(code)
         iop = InstObjParams(name, Name, 'Priv', cblk, opt_flags)
         header_output = BasicDeclare.subst(iop)
@@ -142,7 +135,7 @@ def format Priv(code, *opt_flags) {{
             header_output += BasicDeclare.subst(imm_iop)
             decoder_output += BasicConstructor.subst(imm_iop)
             exec_output += PrivExecute.subst(imm_iop)
-            decode_block = Rb2OrImm13Decode.subst(iop)
+            decode_block = ROrImmDecode.subst(iop)
         else:
             decode_block = BasicDecode.subst(iop)
 }};
@@ -152,8 +145,8 @@ def format PrivTick(code, *opt_flags) {{
         uses_imm = (code.find('Rs2_or_imm13') != -1)
         if uses_imm:
             orig_code = code
-            code = re.sub(r'Rs2_or_imm', 'Rs2', orig_code)
-            imm_code = re.sub(r'Rs2_or_imm(\.\w+)?', 'imm', orig_code)
+            code = re.sub(r'Rs2_or_imm13', 'Rs2', orig_code)
+            imm_code = re.sub(r'Rs2_or_imm13(\.\w+)?', 'imm', orig_code)
         cblk = CodeBlock(code)
         iop = InstObjParams(name, Name, 'PrivTick', cblk, opt_flags)
         header_output = BasicDeclare.subst(iop)
@@ -166,7 +159,7 @@ def format PrivTick(code, *opt_flags) {{
             header_output += BasicDeclare.subst(imm_iop)
             decoder_output += BasicConstructor.subst(imm_iop)
             exec_output += PrivTickExecute.subst(imm_iop)
-            decode_block = Rb2OrImm13Decode.subst(iop)
+            decode_block = Rb2OrImmDecode.subst(iop)
         else:
             decode_block = BasicDecode.subst(iop)
 }};
diff --git a/arch/sparc/isa_traits.hh b/arch/sparc/isa_traits.hh
index 0955abb3a..4886da7cf 100644
--- a/arch/sparc/isa_traits.hh
+++ b/arch/sparc/isa_traits.hh
@@ -98,6 +98,11 @@ namespace SparcISA
     typedef uint32_t MachInst;
     typedef uint64_t ExtMachInst;
 
+    inline ExtMachInst
+    makeExtMI(MachInst inst, const Addr &pc) {
+        return ExtMachInst(inst);
+    }
+
     const int NumIntRegs = 32;
     const int NumFloatRegs = 64;
     const int NumMiscRegs = 32;