Basic cleanup pass to get rid of a few things that made the Python

configuration unnecessarily awkward.  Biggest changes are:

- External and internal object names now match in all cases.  The
macros still allow them to be different; the only reason I didn't
get rid of that is that the macros themselves should be going away
soon.  In the few conflicting cases, I sometimes renamed the C++ object
and sometimes renamed the config object.  The latter sets of substitions
are:

s/BaseBus/Bus/;
s/MemoryObject/FunctionalMemory/;
s/MemoryControl/MemoryController/;
s/FUPool/FuncUnitPool/;

- SamplingCPU is temporarily broken... we need to change the model
of how this works in the .ini file.  Having it as a CPU proxy is
really awkward.

arch/alpha/alpha_memory.cc:
arch/alpha/alpha_memory.hh:
cpu/simple_cpu/simple_cpu.cc:
sim/process.cc:
    Rename objects to match config name.
cpu/base_cpu.cc:
    Uncomment SimObject define since SamplingCPU no longer
    does this for us.
dev/ethertap.cc:
    Use unsigned instead of uint16_t for params.
kern/tru64/tru64_system.cc:
    Use unsigned instead of uint64_t for init_param param.
test/paramtest.cc:
    Fix old SimObjectParam.

--HG--
extra : convert_revision : 378ebbc6a71ad0694501d09979a44d111a59e8dc

2 files changed, 46 insertions, 46 deletions

diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc
index d1b152f73..13cdb1d73 100644
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/alpha_memory.cc
@@ -44,14 +44,14 @@ using namespace std;
 //
 //  Alpha TLB
 //
-AlphaTlb::AlphaTlb(const string &name, int s)
+AlphaTLB::AlphaTLB(const string &name, int s)
     : SimObject(name), size(s), nlu(0)
 {
     table = new AlphaISA::PTE[size];
     memset(table, 0, sizeof(AlphaISA::PTE[size]));
 }
 
-AlphaTlb::~AlphaTlb()
+AlphaTLB::~AlphaTLB()
 {
     if (table)
         delete [] table;
@@ -59,7 +59,7 @@ AlphaTlb::~AlphaTlb()
 
 // look up an entry in the TLB
 AlphaISA::PTE *
-AlphaTlb::lookup(Addr vpn, uint8_t asn) const
+AlphaTLB::lookup(Addr vpn, uint8_t asn) const
 {
     DPRINTF(TLB, "lookup %#x\n", vpn);
 
@@ -83,7 +83,7 @@ AlphaTlb::lookup(Addr vpn, uint8_t asn) const
 
 
 void
-AlphaTlb::checkCacheability(MemReqPtr &req)
+AlphaTLB::checkCacheability(MemReqPtr &req)
 {
     // in Alpha, cacheability is controlled by upper-level bits of the
     // physical address
@@ -111,7 +111,7 @@ AlphaTlb::checkCacheability(MemReqPtr &req)
 
 // insert a new TLB entry
 void
-AlphaTlb::insert(Addr vaddr, AlphaISA::PTE &pte)
+AlphaTLB::insert(Addr vaddr, AlphaISA::PTE &pte)
 {
     if (table[nlu].valid) {
         Addr oldvpn = table[nlu].tag;
@@ -145,7 +145,7 @@ AlphaTlb::insert(Addr vaddr, AlphaISA::PTE &pte)
 }
 
 void
-AlphaTlb::flushAll()
+AlphaTLB::flushAll()
 {
     memset(table, 0, sizeof(AlphaISA::PTE[size]));
     lookupTable.clear();
@@ -153,7 +153,7 @@ AlphaTlb::flushAll()
 }
 
 void
-AlphaTlb::flushProcesses()
+AlphaTLB::flushProcesses()
 {
     PageTable::iterator i = lookupTable.begin();
     PageTable::iterator end = lookupTable.end();
@@ -173,7 +173,7 @@ AlphaTlb::flushProcesses()
 }
 
 void
-AlphaTlb::flushAddr(Addr vaddr, uint8_t asn)
+AlphaTLB::flushAddr(Addr vaddr, uint8_t asn)
 {
     Addr vpn = VA_VPN(vaddr);
 
@@ -201,7 +201,7 @@ AlphaTlb::flushAddr(Addr vaddr, uint8_t asn)
 
 
 void
-AlphaTlb::serialize(ostream &os)
+AlphaTLB::serialize(ostream &os)
 {
     SERIALIZE_SCALAR(size);
     SERIALIZE_SCALAR(nlu);
@@ -213,7 +213,7 @@ AlphaTlb::serialize(ostream &os)
 }
 
 void
-AlphaTlb::unserialize(Checkpoint *cp, const string &section)
+AlphaTLB::unserialize(Checkpoint *cp, const string &section)
 {
     UNSERIALIZE_SCALAR(size);
     UNSERIALIZE_SCALAR(nlu);
@@ -231,13 +231,13 @@ AlphaTlb::unserialize(Checkpoint *cp, const string &section)
 //
 //  Alpha ITB
 //
-AlphaItb::AlphaItb(const std::string &name, int size)
-    : AlphaTlb(name, size)
+AlphaITB::AlphaITB(const std::string &name, int size)
+    : AlphaTLB(name, size)
 {}
 
 
 void
-AlphaItb::regStats()
+AlphaITB::regStats()
 {
     hits
         .name(name() + ".hits")
@@ -256,7 +256,7 @@ AlphaItb::regStats()
 }
 
 void
-AlphaItb::fault(Addr pc, ExecContext *xc) const
+AlphaITB::fault(Addr pc, ExecContext *xc) const
 {
     uint64_t *ipr = xc->regs.ipr;
 
@@ -269,7 +269,7 @@ AlphaItb::fault(Addr pc, ExecContext *xc) const
 
 
 Fault
-AlphaItb::translate(MemReqPtr &req) const
+AlphaITB::translate(MemReqPtr &req) const
 {
     InternalProcReg *ipr = req->xc->regs.ipr;
 
@@ -287,7 +287,7 @@ AlphaItb::translate(MemReqPtr &req) const
         if (!validVirtualAddress(req->vaddr)) {
             fault(req->vaddr, req->xc);
             acv++;
-            return Itb_Acv_Fault;
+            return ITB_Acv_Fault;
         }
 
         // Check for "superpage" mapping: when SP<1> is set, and
@@ -299,7 +299,7 @@ AlphaItb::translate(MemReqPtr &req) const
             if (ICM_CM(ipr[AlphaISA::IPR_ICM]) != AlphaISA::mode_kernel) {
                 fault(req->vaddr, req->xc);
                 acv++;
-                return Itb_Acv_Fault;
+                return ITB_Acv_Fault;
             }
 
             req->paddr = req->vaddr & PA_IMPL_MASK;
@@ -311,7 +311,7 @@ AlphaItb::translate(MemReqPtr &req) const
             if (!pte) {
                 fault(req->vaddr, req->xc);
                 misses++;
-                return Itb_Fault_Fault;
+                return ITB_Fault_Fault;
             }
 
             req->paddr = PA_PFN2PA(pte->ppn) + VA_POFS(req->vaddr & ~3);
@@ -321,7 +321,7 @@ AlphaItb::translate(MemReqPtr &req) const
                 // instruction access fault
                 fault(req->vaddr, req->xc);
                 acv++;
-                return Itb_Acv_Fault;
+                return ITB_Acv_Fault;
             }
 
             hits++;
@@ -341,12 +341,12 @@ AlphaItb::translate(MemReqPtr &req) const
 //
 //  Alpha DTB
 //
-AlphaDtb::AlphaDtb(const std::string &name, int size)
-    : AlphaTlb(name, size)
+AlphaDTB::AlphaDTB(const std::string &name, int size)
+    : AlphaTLB(name, size)
 {}
 
 void
-AlphaDtb::regStats()
+AlphaDTB::regStats()
 {
     read_hits
         .name(name() + ".read_hits")
@@ -415,7 +415,7 @@ AlphaDtb::regStats()
 }
 
 void
-AlphaDtb::fault(Addr vaddr, uint64_t flags, ExecContext *xc) const
+AlphaDTB::fault(Addr vaddr, uint64_t flags, ExecContext *xc) const
 {
     uint64_t *ipr = xc->regs.ipr;
 
@@ -439,7 +439,7 @@ AlphaDtb::fault(Addr vaddr, uint64_t flags, ExecContext *xc) const
 }
 
 Fault
-AlphaDtb::translate(MemReqPtr &req, bool write) const
+AlphaDTB::translate(MemReqPtr &req, bool write) const
 {
     RegFile *regs = &req->xc->regs;
     Addr pc = regs->pc;
@@ -553,7 +553,7 @@ AlphaDtb::translate(MemReqPtr &req, bool write) const
 }
 
 AlphaISA::PTE &
-AlphaTlb::index(bool advance)
+AlphaTLB::index(bool advance)
 {
     AlphaISA::PTE *pte = &table[nlu];
 
@@ -563,43 +563,43 @@ AlphaTlb::index(bool advance)
     return *pte;
 }
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaItb)
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
 
     Param<int> size;
 
-END_DECLARE_SIM_OBJECT_PARAMS(AlphaItb)
+END_DECLARE_SIM_OBJECT_PARAMS(AlphaITB)
 
-BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaItb)
+BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaITB)
 
     INIT_PARAM_DFLT(size, "TLB size", 48)
 
-END_INIT_SIM_OBJECT_PARAMS(AlphaItb)
+END_INIT_SIM_OBJECT_PARAMS(AlphaITB)
 
 
-CREATE_SIM_OBJECT(AlphaItb)
+CREATE_SIM_OBJECT(AlphaITB)
 {
-    return new AlphaItb(getInstanceName(), size);
+    return new AlphaITB(getInstanceName(), size);
 }
 
-REGISTER_SIM_OBJECT("AlphaITB", AlphaItb)
+REGISTER_SIM_OBJECT("AlphaITB", AlphaITB)
 
-BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDtb)
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
 
     Param<int> size;
 
-END_DECLARE_SIM_OBJECT_PARAMS(AlphaDtb)
+END_DECLARE_SIM_OBJECT_PARAMS(AlphaDTB)
 
-BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDtb)
+BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
 
     INIT_PARAM_DFLT(size, "TLB size", 64)
 
-END_INIT_SIM_OBJECT_PARAMS(AlphaDtb)
+END_INIT_SIM_OBJECT_PARAMS(AlphaDTB)
 
 
-CREATE_SIM_OBJECT(AlphaDtb)
+CREATE_SIM_OBJECT(AlphaDTB)
 {
-    return new AlphaDtb(getInstanceName(), size);
+    return new AlphaDTB(getInstanceName(), size);
 }
 
-REGISTER_SIM_OBJECT("AlphaDTB", AlphaDtb)
+REGISTER_SIM_OBJECT("AlphaDTB", AlphaDTB)
 
diff --git a/arch/alpha/alpha_memory.hh b/arch/alpha/alpha_memory.hh
index 999eec228..12196c44b 100644
--- a/arch/alpha/alpha_memory.hh
+++ b/arch/alpha/alpha_memory.hh
@@ -37,7 +37,7 @@
 
 class ExecContext;
 
-class AlphaTlb : public SimObject
+class AlphaTLB : public SimObject
 {
   protected:
     typedef std::multimap<Addr, int> PageTable;
@@ -51,8 +51,8 @@ class AlphaTlb : public SimObject
     AlphaISA::PTE *lookup(Addr vpn, uint8_t asn) const;
 
   public:
-    AlphaTlb(const std::string &name, int size);
-    virtual ~AlphaTlb();
+    AlphaTLB(const std::string &name, int size);
+    virtual ~AlphaTLB();
 
     int getsize() const { return size; }
 
@@ -77,7 +77,7 @@ class AlphaTlb : public SimObject
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 };
 
-class AlphaItb : public AlphaTlb
+class AlphaITB : public AlphaTLB
 {
   protected:
     mutable Statistics::Scalar<> hits;
@@ -89,13 +89,13 @@ class AlphaItb : public AlphaTlb
     void fault(Addr pc, ExecContext *xc) const;
 
   public:
-    AlphaItb(const std::string &name, int size);
+    AlphaITB(const std::string &name, int size);
     virtual void regStats();
 
     Fault translate(MemReqPtr &req) const;
 };
 
-class AlphaDtb : public AlphaTlb
+class AlphaDTB : public AlphaTLB
 {
   protected:
     mutable Statistics::Scalar<> read_hits;
@@ -115,7 +115,7 @@ class AlphaDtb : public AlphaTlb
     void fault(Addr pc, uint64_t flags, ExecContext *xc) const;
 
   public:
-    AlphaDtb(const std::string &name, int size);
+    AlphaDTB(const std::string &name, int size);
     virtual void regStats();
 
     Fault translate(MemReqPtr &req, bool write) const;