summaryrefslogtreecommitdiff
path: root/arch
diff options
context:
space:
mode:
authorRon Dreslinski <rdreslin@umich.edu>2004-01-14 16:21:49 -0500
committerRon Dreslinski <rdreslin@umich.edu>2004-01-14 16:21:49 -0500
commitb3788280f6e630e225fa7e4c666a8d2973227308 (patch)
tree815ecb634b7b7d417f0dd486965626277d560d69 /arch
parent54782bfb30a275b8294c3a993e420bc0d2b97725 (diff)
downloadgem5-b3788280f6e630e225fa7e4c666a8d2973227308.tar.xz
Add memory space implemented for range 0xffff00188
--HG-- extra : convert_revision : ce17505cb97bf9985fd1f4992df89113a5ea3bf5
Diffstat (limited to 'arch')
-rw-r--r--arch/alpha/alpha_memory.cc12
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc
index d934299b8..84b3d5840 100644
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/alpha_memory.cc
@@ -90,8 +90,16 @@ AlphaTlb::checkCacheability(MemReqPtr req)
if (req->paddr & PA_UNCACHED_BIT) {
if (PA_IPR_SPACE(req->paddr)) {
// IPR memory space not implemented
- if (!req->xc->misspeculating())
- panic("IPR memory space not implemented! PA=%x\n", req->paddr);
+ if (!req->xc->misspeculating()) {
+ switch (req->paddr) {
+ case 0xFFFFF00188:
+ req->data = 0;
+ break;
+
+ default:
+ panic("IPR memory space not implemented! PA=%x\n", req->paddr);
+ }
+ }
} else {
// mark request as uncacheable
req->flags |= UNCACHEABLE;