infinitesimal small baby steps toward MIPS actually working

arch/mips/isa/formats/branch.isa:
    let user know that we alter r31 in disassembly
arch/mips/isa_traits.cc:
    add copyRegs function ...
    comment out serialize float code for now
arch/mips/isa_traits.hh:
    make FloatRegFile a class ... change values of architectural regs
arch/mips/process.cc:
    change MIPS to Mips
base/loader/elf_object.cc:
    get global pointer initialized to a value
base/loader/elf_object.hh:
    Add global_ptr to elf_object constructor
base/loader/object_file.hh:
    MIPS to Mips
base/traceflags.py:
    SimpleCPU trace flag
cpu/simple/cpu.cc:
    DPRINTF flags for SimpleCPU
cpu/static_inst.hh:
    Add Decoder functions to static_inst.hh

--HG--
extra : convert_revision : 0544a8524d3fe4229428cb06822f7da208c72459

1 files changed, 3 insertions, 1 deletions

diff --git a/base/loader/object_file.hh b/base/loader/object_file.hh
index 08a51863e..309089728 100644
--- a/base/loader/object_file.hh
+++ b/base/loader/object_file.hh
@@ -44,7 +44,7 @@ class ObjectFile
         UnknownArch,
         Alpha,
         SPARC,
-        MIPS
+        Mips
     };
 
     enum OpSys {
@@ -95,9 +95,11 @@ class ObjectFile
     Section bss;
 
     bool loadSection(Section *sec, TranslatingPort *memPort, bool loadPhys);
+    void setGlobalPointer(Addr global_ptr) { globalPtr = global_ptr; }
 
   public:
     Addr entryPoint() const { return entry; }
+
     Addr globalPointer() const { return globalPtr; }
 
     Addr textBase() const { return text.baseAddr; }