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| author | Ron Dreslinski <rdreslin@umich.edu> | 2006-02-20 23:56:10 -0500 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-02-20 23:56:10 -0500 |
| commit | 33913542859fa2bef15765009ae33d5e724bb0b0 (patch) | |
| tree | 0a21e20c5e18eb64ff74e2abff61298d3379653e /base/loader/object_file.hh | |
| parent | d96de69abc02b40e1dec4843a7a7b7e30749f4fa (diff) | |
| download | gem5-33913542859fa2bef15765009ae33d5e724bb0b0.tar.xz | |
Make loaders use translation port instead of proxy memory.
Also start compiling Simple CPU again.
SConscript:
Start Compiling Simple CPU as well
base/loader/aout_object.cc:
base/loader/aout_object.hh:
base/loader/ecoff_object.cc:
base/loader/ecoff_object.hh:
base/loader/elf_object.cc:
base/loader/elf_object.hh:
base/loader/object_file.hh:
sim/process.cc:
sim/process.hh:
Convert loaders to used translation port instead of proxy memory
--HG--
extra : convert_revision : 63275071f6a0e0d71935641205b203d94381ee44
Diffstat (limited to 'base/loader/object_file.hh')
| -rw-r--r-- | base/loader/object_file.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/base/loader/object_file.hh b/base/loader/object_file.hh index 091e5493c..1d750e341 100644 --- a/base/loader/object_file.hh +++ b/base/loader/object_file.hh @@ -31,7 +31,7 @@ #include "targetarch/isa_traits.hh" // for Addr -class Memory; +class TranslatingPort; class SymbolTable; class ObjectFile @@ -67,7 +67,7 @@ class ObjectFile void close(); - virtual bool loadSections(Memory *mem, bool loadPhys = false) = 0; + virtual bool loadSections(TranslatingPort *memPort, bool loadPhys = false) = 0; virtual bool loadGlobalSymbols(SymbolTable *symtab) = 0; virtual bool loadLocalSymbols(SymbolTable *symtab) = 0; |