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| author | Alec Roelke <ar4jc@virginia.edu> | 2016-11-30 17:10:28 -0500 |
|---|---|---|
| committer | Alec Roelke <ar4jc@virginia.edu> | 2016-11-30 17:10:28 -0500 |
| commit | 126c0360e2efd9588f38128bad94c7fa82c79f25 (patch) | |
| tree | 0bd6e50edf0a0f9d0b961bb0c0dd0926b2635013 /build_opts/RISCV | |
| parent | 535e6c5fa4f05ae17b8b0ce6c4fd85e2cfb0189b (diff) | |
| download | gem5-126c0360e2efd9588f38128bad94c7fa82c79f25.tar.xz | |
riscv: [Patch 5/5] Added missing support for timing CPU models
Last of five patches adding RISC-V to GEM5. This patch adds support for
timing, minor, and detailed CPU models that was missing in the last four,
which basically consists of handling timing-mode memory accesses and
telling the minor and detailed models what a no-op instruction should
be (addi zero, zero, 0).
Patches 1-4 introduced RISC-V and implemented the base instruction set,
RV64I, and added the multiply, floating point, and atomic memory
extensions, RV64MAFD.
[Fixed compatibility with edit from patch 1.]
[Fixed compatibility with hg copy edit from patch 1.]
[Fixed some style errors in locked_mem.hh.]
Signed-off by: Alec Roelke
Signed-off by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'build_opts/RISCV')
| -rw-r--r-- | build_opts/RISCV | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/build_opts/RISCV b/build_opts/RISCV index 3b5053a79..38abd9216 100644 --- a/build_opts/RISCV +++ b/build_opts/RISCV @@ -1,3 +1,3 @@ TARGET_ISA = 'riscv' -CPU_MODELS = 'AtomicSimpleCPU' +CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,MinorCPU,O3CPU' PROTOCOL = 'MI_example' |