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authorAli Saidi <Ali.Saidi@ARM.com>2010-11-15 14:04:04 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2010-11-15 14:04:04 -0600
commit2a3cefe15115a094eadd74a659a2f919a83ac6a4 (patch)
tree6a7750f4469587f5bad4cd68f4efe85fc7c34558 /build_opts
parent745df74fe0ee57444487c7a231ce02a96244e48d (diff)
downloadgem5-2a3cefe15115a094eadd74a659a2f919a83ac6a4.tar.xz
ARM: Compile O3 CPU by default
Diffstat (limited to 'build_opts')
-rw-r--r--build_opts/ARM_FS2
-rw-r--r--build_opts/ARM_SE2
2 files changed, 2 insertions, 2 deletions
diff --git a/build_opts/ARM_FS b/build_opts/ARM_FS
index 9d518142d..f6b2d9e21 100644
--- a/build_opts/ARM_FS
+++ b/build_opts/ARM_FS
@@ -1,4 +1,4 @@
TARGET_ISA = 'arm'
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU'
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
FULL_SYSTEM = 1
PROTOCOL = 'MI_example'
diff --git a/build_opts/ARM_SE b/build_opts/ARM_SE
index 5019edb0a..1d89b87a3 100644
--- a/build_opts/ARM_SE
+++ b/build_opts/ARM_SE
@@ -1,4 +1,4 @@
TARGET_ISA = 'arm'
FULL_SYSTEM = 0
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU'
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
PROTOCOL = 'MI_example'