diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2011-02-01 18:28:41 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2011-02-01 18:28:41 -0800 |
| commit | 119f5f8e94e673b1495dccce03b54773dc18afea (patch) | |
| tree | ff11fb58d39d12bd7c4fa5d94f629d718fe4e2ec /configs/common/CacheConfig.py | |
| parent | 4b4cd0303ea0e3b23e641933dbf0da57d1483764 (diff) | |
| download | gem5-119f5f8e94e673b1495dccce03b54773dc18afea.tar.xz | |
X86: Add L1 caches for the TLB walkers.
Small L1 caches are connected to the TLB walkers when caches are used. This
allows them to participate in the coherence protocol properly.
Diffstat (limited to 'configs/common/CacheConfig.py')
| -rw-r--r-- | configs/common/CacheConfig.py | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/configs/common/CacheConfig.py b/configs/common/CacheConfig.py index 075f6d235..c4f91fd9e 100644 --- a/configs/common/CacheConfig.py +++ b/configs/common/CacheConfig.py @@ -43,8 +43,14 @@ def config_cache(options, system): for i in xrange(options.num_cpus): if options.caches: - system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), - L1Cache(size = '64kB')) + if buildEnv['TARGET_ISA'] == 'x86': + system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), + L1Cache(size = '64kB'), + PageTableWalkerCache(), + PageTableWalkerCache()) + else: + system.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), + L1Cache(size = '64kB')) if options.l2cache: system.cpu[i].connectMemPorts(system.tol2bus) else: |